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mjuneja2007's avatar
mjuneja2007
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Agilex board POF file programming - causing lspci enumeration problem

Hello

I have generated a SOF file using CXL IP example design and then converted the same into POF using below settings and these steps 3.1.7.5.1. Converting .sof to .pof File

Configuration mode: AVST x8

Device selected: CFI_2Gb

- Options Edit partition

Address Mode = Start, Start Address = 0x00010000

- P1 partition (newly added partition)

Address Mode = Start, Start Address = 0x00020000

Input file - SOF file added

When I generate, I am getting 2 files

<design_name> .pof and <design_name>_pof.map.

After that I am programming the pof file in my Agilex board(DK-DEV-AGI027-RA) using these steps. 3.4. How to Program the Generated POF Image

But when I reboot the host after programming, Agilex board doesn't enumerate in lspci, even JTAG scan chain is not able to detect the device in Programmer Tool, so I have to program the fpga recovery pof file to again enumerate the board and make it detectable in JTAG.

Can you tell me what the possible issue could be here.

Thanks & regards

Madhur Juneja

Board Debug
Fpga Devkit

4 Replies

  • Farabi_Altera's avatar
    Farabi_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hello,


    Is the configuration successfully completed? Can you see the CONF_DONE signal turn HIGH?


    regards

    Farabi


    • mjuneja2007's avatar
      mjuneja2007
      Icon for Occasional Contributor rankOccasional Contributor
      1 year ago

      Hello Farabi

      No configuration is not completing. I even tried to load the same SOF file using Signal Tap Analyzer tool, configuration never finishes.

      I also checked the below

      1. pin mapping of CXL IP, it is at IO bank 14C as per schematic.

      2. Pin mapping of refclk4 (AN61) was wrong as per schematic which I corrected to N45.

      3. JTAG related constraints in sdc file are kept same as generated during example design.

      Note:- SOF files without CXL IP are configuring the FPGA successfully without any problem.

      Can you please suggest the possible issues here.

      regards

      Madhur

  • mjuneja2007's avatar
    mjuneja2007
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hi Farabi

    By updating Linear Format N (in Power Management & VID) from -13 to -12, the issue of "SOF Configuration not completing" resolves and even CONF_DONE signal turns high (as confirmed in Configuration Debugger).

    But when I convert this SOF into POF and put it in Agilex board flash memory. Then after rebooting, host doesn't turns up :(.

    regards

    Madhur

  • Farabi_Altera's avatar
    Farabi_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hello,


    I have escalated this issue to PCIe/CXL subject matter expert. We will continue to support you on case 06613600.

    I am closing this case.


    regards,

    Farabi