Forum Discussion
mjuneja2007
Occasional Contributor
Occasional ContributorAgilex board POF file programming - causing lspci enumeration problem
Hello I have generated a SOF file using CXL IP example design and then converted the same into POF using below settings and these steps 3.1.7.5.1. Converting .sof to .pof File Configuration mode: ...
Farabi_Altera
Regular Contributor
Regular ContributorHello,
Is the configuration successfully completed? Can you see the CONF_DONE signal turn HIGH?
regards
Farabi
mjuneja2007Occasional Contributor
Occasional ContributorHello Farabi
No configuration is not completing. I even tried to load the same SOF file using Signal Tap Analyzer tool, configuration never finishes.
I also checked the below
1. pin mapping of CXL IP, it is at IO bank 14C as per schematic.
2. Pin mapping of refclk4 (AN61) was wrong as per schematic which I corrected to N45.
3. JTAG related constraints in sdc file are kept same as generated during example design.
Note:- SOF files without CXL IP are configuring the FPGA successfully without any problem.
Can you please suggest the possible issues here.
regards
Madhur
