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mjuneja2007's avatar
mjuneja2007
Icon for Occasional Contributor rankOccasional Contributor
6 months ago

Agilex board POF file programming - causing lspci enumeration problem

Hello I have generated a SOF file using CXL IP example design and then converted the same into POF using below settings and these steps 3.1.7.5.1. Converting .sof to .pof File Configuration mode: ...
Board Debug
Fpga Devkit
Farabi's avatar
Farabi
Icon for Regular Contributor rankRegular Contributor
6 months ago

Hello,


Is the configuration successfully completed? Can you see the CONF_DONE signal turn HIGH?


regards

Farabi


mjuneja2007's avatar
mjuneja2007
Icon for Occasional Contributor rankOccasional Contributor
6 months ago

Hello Farabi

No configuration is not completing. I even tried to load the same SOF file using Signal Tap Analyzer tool, configuration never finishes.

I also checked the below

1. pin mapping of CXL IP, it is at IO bank 14C as per schematic.

2. Pin mapping of refclk4 (AN61) was wrong as per schematic which I corrected to N45.

3. JTAG related constraints in sdc file are kept same as generated during example design.

Note:- SOF files without CXL IP are configuring the FPGA successfully without any problem.

Can you please suggest the possible issues here.

regards

Madhur