Most RecentWhy am I seeing a linkup problem when using consortium mode for F-tile Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) and Dynamic Reconfiguration enabled designs?Why do o_tx_pll_locked and o_rx_is_lockedtoref toggle in simulation when using PMA clocking mode for Agilex® 3 and Agilex® 5 FPGAs in Quartus® Prime Pro Edition version 25.1.1 or earlier?Why does the o_tx_pll_locked signal of the GTS transceivers show an asserted state when there is no input reference clock for Agilex® 5 FPGA devices in the Quartus® Prime Pro Edition Software version 24.1 and 24.2?Why does a compilation error happen when using the IOPLL in the HVIO bank in place of a GTS System PLL for the PMA/FEC Direct PHY IP and all other protocol IPs for the Agilex® 3 FPGA and Agilex® 5 FPGA designs?Why are there errors while generating an example design using GTS Transceiver with Dynamic Reconfiguration (DR) between two rates in the Quartus® Prime Pro Edition software version 25.1?Why is the link-up failure observed for the F-tile Dynamic Reconfiguration Suite IP with Auto-Negotiation and Link Training (AN/LT) enabled designs when trying to skip Link Training (LT)?Why is my hardware test failing when using GTS Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) and ECC enabled?Why is my IP license checked out and not released after using the Signal Tap Logic Analyzer?Error: Tcl error: DVR_API: List of error MSGs are {list element in braces followed by "]" instead of spaceWhy are HVIO pins not having the optional function SYSPLLREFCLK allowed to be assigned as a reference clock for the System PLL for the Agilex® 3 FPGA and Agilex® 5 FPGA GTS transceiver in the Quartus® Prime Pro Edition software version 25.1 and earlier?
