Most RecentWhy does the RX alignment lock remain low when simulating the E-Tile Hard IP for Ethernet in 100G with RS(528,514) FEC and 100G with RS(544,514) FEC design examples using the Synopsys* VCS* / VCS* MX simulation tools?Why am I observing failures to read base Channel 0 in a multi-lane design for the GTS Serial Lite IV IP?Why is the Slot Clock Configuration parameter invisible when the PCIe0/PCIe1 Port Mode parameter is set to Native Endpoint in the GTS AXI Streaming FPGA IP for PCI Express*?Why is a flickering video output observed for the Agilex® DisplayPort FPGA IP when programming the SST Parallel Loopback Design Example on hardware?Why is there a mismatch between the sideband information field of the Scalable Scatter-Gather DMA IP D2H ST responder descriptor and the error bit of the d2h_st_tuser signal?Why is the R-tile stuck in Reset after configuration for Agilex™ 7 FPGA devices with package codes “R31A” and “R31E”?Why are there ongoing DMA transactions at the Scalable Scatter-Gather DMA IP's device port even after the completion of the device port soft pause and soft reset sequence flow?Why am I seeing linkup problem when switching from DAC to AOC cable for the F-tile Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) and Dynamic Reconfiguration enabled FHT designs.Is there a reference on how to enable internal serial loopback mode for the GTS Transceiver PMA link for usage with data rate < 7Gbps?Why do I see link failure after a few resets when the GTS Transceiver PMA link is placed under internal serial loopback mode?
