Why is the R-tile stuck in Reset after configuration for Agilex™ 7 FPGA devices with package codes “R31A” and “R31E”?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 25.1 and earlier, the R-tile fails to be configured on designs that enable at least one R-tile and one F-tile in Agilex™ 7 FPGA devices with package codes R31A and R31E, even if the configuration status of the Agilex™ 7 FPGA device reports as successful. This affects the functionality of the R-tile PCI Express and CXL IPs, where the PCI Express link will fail to train and enumerate. F-tile functionality is not affected.

This problem can occur in all configuration modes. 

For devices with the package code "R31E,"  the following design configurations are not affected. Note that tiles near the SDM block are positioned on the left side.

• R-tile at the top left and the F-tile at the bottom right
• R-tiles at both the top left and bottom left, and the F-tile is located at either or both of the top right and bottom right
• R-tiles at both the top left and bottom left

Resolution

To work around this problem, a patch is available to download and install for the following versions of the Quartus® Prime Pro Edition software:

 

Quartus® Prime Pro Edition software version 25.1

• Patch 0.20 for the Quartus® Prime Pro Edition Software version 25.1 for Windows (.exe)
• Patch 0.20 for the Quartus® Prime Pro Edition Software version 25.1 for Linux (.run)
• Readme for Patch 0.20 for the Quartus® Prime Pro Edition Software version 25.1 (.txt)

 

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.