Why does the RX alignment lock remain low when simulating the E-Tile Hard IP for Ethernet in 100G with RS(528,514) FEC and 100G with RS(544,514) FEC design examples using the Synopsys* VCS* / VCS* MX simulation tools?

Description

When using the latest versions of the Synopsys* VCS* / VCS* MX simulator, RX alignment lock is remaining low for both the 100G with RS(528,514) FEC and the 100G with RS(544,514) FEC design examples of the E-Tile Ethernet Hard IP due to the presence of switch "-deraceclockdata" in the USER_DEFINED_ELAB_OPTIONS in the sim script file run_vcs.sh.

This problem applies to E-Tile Ethernet Hard IP in both Stratix® 10 FPGA and Agilex™ 7 FPGA devices and is limited to the 100G Design Examples.

Resolution

To workaround this problem, remove the option "-deraceclockdata" from the USER_DEFINED_ELAB_OPTIONS in the sim script file run_vcs.sh located in the testbench simulation directory <design_example_dir>/example_testbench.

This problem is planned to be fixed in a future release of the Quartus® Prime Pro Software Edition.