Why do o_tx_pll_locked and o_rx_is_lockedtoref toggle in simulation when using PMA clocking mode for Agilex™ 3 and 5 FPGAs in Quartus® Prime Pro Edition version 25.1.1 or earlier?

Description

Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1 and earlier, both o_tx_pll_locked and o_rx_is_lockedtoref signals are toggling due to multiple resets being asserted and de-asserted during bootup when running simulation using PMA clocking mode.

This happens in simulation due to the PLL settings getting corrupted because Soft Reset Controller (SRC) receives a reset request from the user and, in turn, asserts the PMA resets before certain attributes are loaded, which happens after 4480ns. 

Resolution

To work around this problem, do not apply any resets before 4480ns in simulations for PMA clocking mode.

This problem will be fixed in a future release of the Quartus® Prime Pro Edition software.