Why are HVIO pins not having the optional function SYSPLLREFCLK allowed to be assigned as a reference clock for the System PLL for the Agilex™ 3 FPGA and Agilex™ 5 FPGA GTS transceiver in the Quartus® Prime Pro Edition software version 25.1 and earlier?

Description

Due to a problem in the Quartus® Prime Pro Edition software version 25.1 and earlier, it incorrectly allows the assignment of other HVIO pins without the SYSPLLREFCLK description.
An example of a correct selection would be the HVIO pin with the following optional functions listed: HVIO_5B_1, SYSPLLREFCLK_L1A_0, TXCLK1, Data_Ctrl1. This is the correct pin to select as a reference clock for the system PLL in the GTS transceiver bank 1A.
An example of an incorrect selection would be an HVIO pin without the SYSPLLREFCLK optional function listing: HVIO_5B_20, TXCLK20, Data_Ctrl20. Therefore, selecting this as a reference clock pin for system PLL is incorrect, but the Quartus® Prime Pro Edition software does not currently report this as an error.

Resolution

To work around this problem, refer to the device pinout and pin connection guidelines and ensure it has the correct SYSPLLREFCLK optional function when selecting an HVIO pin as a system PLL reference clock.

• Agilex 5 Device Pin-out Files
• Agilex 5 Pin Connection Guidelines

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.