Why does the o_tx_pll_locked signal of the GTS transceivers show an asserted state when there is no input reference clock for Agilex™ 5 FPGA devices in the Quartus® Prime Pro Edition Software version 24.1 and 24.2?

Description

Due to a problem in the Quartus® Prime Pro Edition Software versions 24.1 and 24.2, the o_tx_pll_locked signal does not reflect the correct status of the TX PLLs in the GTS transceiver. This causes the o_tx_pll_locked signal to be incorrectly asserted without an input reference clock.

Additionally, when a loss of reference clock occurs, the o_tx_pll_locked status signal will not go low. This deviates from the expected behavior described in section 3.8.9 of the GTS Transceiver PHY user guide.
The only supported condition is ensuring the input reference clock is always present.
 

Resolution

There is no workaround currently.

This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.