Why does the maximum observed channel-to-channel skew exceed 2 UI + 125 ps in an E-Tile transceiver under NRZ mode, even when TX PMA bonding is enabled?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, you may observe channel-to-channel skew exceeds 2 UI + 125 ps in E-Tile transceivers under NRZ mode even when TX PMA bonding is enabled. Resolution There is no workaround currently, and there is no plan to fix this problem.Why does my Stratix® 10 FPGA device hang when triggering FPGA reconfiguration via nCONFIG pin and Frequency Tamper Detection feature is enabled?
Description In Quartus® Prime Pro Edition Software version 25.1 and earlier, an issue occurs when the physical anti‑tamper feature is enabled using the Frequency Tamper Detection method in combination with an Active Serial configuration scheme. If you initiate a device reconfiguration by pulsing the nCONFIG pin, the Stratix® 10 FPGA may hang and fail to proceed with the reconfiguration process. Resolution You can recover the device by performing a power cycle. This issue is planned to be resolved in a future release of the Quartus® Prime Pro Edition Software.Why is no video output displayed when migrating the F-Tile SDI II FPGA IP Design Example with 12G multi-rate from an older version to Quartus® Prime Pro Edition Software version 25.3.1 patch 1.10 ?
Description Due to an issue in the Quartus® Prime Pro Edition Software Programmer version 25.3.1, users may observe that no SDI II video output is displayed on the receiver side when using the F-tile SDI II FPGA IP Design Example with 12G multi-rate on Agilex® 7 FPGA devices. This issue is caused by forcing lock-to-data. For SDI dynamic reconfiguration designs, manual CDR lock mode with lock-to-ref enabled should be used. Resolution To solve this problem, use below method 1. Open Platform Designer of sdi_rx_sys.qsys 2. Disable fgt_rx_set_locktodata port, Enable fgt_rx_set_locktoref port 3. At System View Should not seeing fgt_rx_set_locktodata port Export fgt_rx_set_locktoref port out 4. Sync info and regenerate HDL 5. Open rx_top.sv file Comment out / remove fgt_rx_set_locktodata Add exported fgt_rx_set_locktoref port and connect to ~rx_set_ltd 6. Save and recompile design This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.
Why does the Interlaken (2nd Generation) Intel® FPGA IP fail to generate an evaluation mode programming file?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.1, the Interlaken (2nd Generation) Intel® FPGA IP doesn't support the Intel® FPGA IP Evaluation Mode for time-limited programming file (.sof) generation. Resolution To work around this problem, follow the steps below: Download a copy of uflex_ilk_tx_ext.ocp and uflex_ilk_rx_regroup_n.ocp files Place a copy of uflex_ilk_tx_ext.ocp under <IP_generation_folder>/altera_uflex_ilk_<xxxx>/synth/uflex_ilk_mac/ Place a copy of uflex_ilk_rx_regroup_n.ocp under <IP_generation_folder>/altera_uflex_ilk_<xxxx>/synth/uflex_ilk_regroup/ Add the lines below to the Intel® Quartus® Prime IP File of your IP variant <IP_generation_folder>/<IP_name>.qip Recompile your design set_global_assignment -library "altera_uflex_ilk_<xxxx>" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_uflex_ilk_<xxxx>/synth/uflex_ilk_mac/uflex_ilk_tx_ext.ocp"] set_global_assignment -library "altera_uflex_ilk_<xxxx>" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_uflex_ilk_<xxxx>/synth/uflex_ilk_regroup/uflex_ilk_rx_regroup_n.ocp"] * Remember to substitute <xxxx> with the four-digit number that was assigned to your IP variant after IP generation This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software 21.2.Why does it take a long time until the SDI II Intel® FPGA IP Receiver detects video standard when receiving SD-SDI video standard?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3 and Standard Edition software version 21.1 and earlier, it might take a long time until the SDI II Intel® FPGA IP Receiver detects video standard when receiving SD-SDI video standard. This problem might occur when the clock sources of the rx_coreclk and the xcvr_refclk in the SDI II Intel FPGA IP are 0 ppm tolerance. Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Standard Edition Software version 18.1. Download and install patch 0.23std from the appropriate link below, then re-generate your programming file. Download patch 0.23std for Windows (Quartus-18.1std-0.23std-windows.exe) Download patch 0.23std for Linux (Quartus-18.1std-0.23std-linux.run) Download the Readme for patch 0.23std (Quartus-18.1std-0.23std-readme.txt) This problem is scheduled to be fixed in a future release of the Intel Quartus Prime Pro/Standard Edition Software.Error: SDC_ENTITY not allowed for EFileKind, must be in {[VERILOG, VERILOG_ENCRYPT, SYSTEM_VERILOG, SYSTEM_VERILOG_ENCRYPT, VERILOG_INCLUDE, SYSTEM_VERILOG_INCLUDE, VHDL, VHDL_ENCRYPT, SDC, MIF, HEX, DAT, QXP, HPS_ISW, PLI_LIBRARY, VPI_LIBRARY, OTHER]}
Description Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 21.1, the error message above may be seen while executing 'generate HDL' for the Error Message Register Unloader Intel® FPGA IP Core when using Intel® Stratix® V, Intel® Arria® V, or Intel® Cyclone® V devices. The full error message is shown below: Error: SDC_ENTITY not allowed for EFileKind, must be in {[VERILOG, VERILOG_ENCRYPT, SYSTEM_VERILOG, SYSTEM_VERILOG_ENCRYPT, VERILOG_INCLUDE, SYSTEM_VERILOG_INCLUDE, VHDL, VHDL_ENCRYPT, SDC, MIF, HEX, DAT, QXP, HPS_ISW, PLI_LIBRARY, VPI_LIBRARY, FLI_LIBRARY, OTHER]} while executing "add_fileset_file $sdc_file SDC_ENTITY PATH $sdc_file {NO_AUTO_INSTANCE_DISCOVERY NO_SDC_PROMOTION}" (procedure "generate_verilog_fileset" line 24) invoked from within "generate_verilog_fileset $name $ifdef_params_list" (procedure "generate_synth" line 9) invoked from within "generate_synth altera_emr_unloader" Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Standard Edition Software version 21.1 Download and install Patch 0.08std for the Intel® Quartus® Prime Standard Edition Software version 21.1 from the appropriate link below: (To download the .run file, right-click on the above link and choose “Save link as”) Intel® Quartus® Prime Standard Edition Software version 21.1 patch: Download patch 0.08std for Windows (.exe) Download patch 0.08std for Linux (.run) Download the Readme for patch 0.08std (.txt) This problem is fixed starting from Intel® Quartus® Prime Standard Edition Software version 22.1.Why can't a valid PMA profile be stored in the Serial Lite IV Intel® FPGA IP?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.4 and earlier, you might not be able to access the PMA adaptation tab and store a valid PMA profile in the Serial Lite IV Intel® FPGA IP. Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software version 21.2. Download and install patch 0.38 from the following links: Intel Quartus Prime Pro Edition Software v21.2 Patch 0.38 for Windows (.exe) Intel Quartus Prime Pro Edition Software v21.2 Patch 0.38 for Linux (.run) ReadMe for Intel Quartus Prime Pro Edition Software v21.2 Patch 0.38 (.txt) This problem is currently scheduled to be resolved in a future release of the Intel Quartus Prime Pro Edition Software.Why does EMIF for HPS LPDDR4 fail calibration on the Agilex™ 5 FPGA and SoC FPGA?
Description In the Quartus® Prime Pro Edition Software 24.3, when configuring the Agilex™ 5 FPGAs and SoC FPGAs with the EMIF for HPS IP and LPDDR4 device implemented as dual rank (2 chip selects), dual channels (i.e., 4 dies each being 16 Gbit in density), calibration can fail. Resolution Please download the Quartus® Prime Pro Edition Software 24.3 patch 0.11 for a fix. This issue is planned to be fixed in a later Quartus® Prime Pro Edition Software release. quartus-24.3-0.11-windows.exe quartus-24.3-0.11-linux.run quartus-24.3-0.11-readme.txtWhy do I see the read data corruption with the Stratix® 10 FPGA QDRII+ IP when the calibration passes consistently?
Description You might observe the read data corruption when there is a large difference in the calibrated DQS-en setting between calibration attempts with the Stratix® 10 FPGA QDRII+ intellectual property (IP). Resolution You can download the patch for Quartus® Prime Software v21.2 release to fix this problem. Please contact Altera support for other Quartus® Prime Software release patches. Readme for the Quartus® Prime Pro Edition Software version 21.2-0.40-readme.txt Patch for the Quartus® Prime Pro Edition Software version 21.2-0.40-windows.exe Patch for the Quartus® Prime Pro Edition Software version 21.2-0.40-linux.runWhy is the TXPLL or CDR unable to achieve lock to reference clock for Agilex™ 5 FPGA designs, which have GTS transceivers and HPS EMIF enabled when using bitstream compiled and generated in the Quartus® Prime Pro Edition Software version 23.4.1 and 24.1?
Description In the Agilex™ 5 FPGA designs, which enable HPS EMIF and IPs using GTS transceivers, the TX PLL or CDR of the GTS transceiver will not be able to lock to its reference clock. This is due to a problem in the Quartus® Prime Pro Edition Software versions 23.4.1 and 24.1, which incorrectly sets the reference clock mux. In designs with IPs using GTS transceivers only without HPS EMIF enabled, the GTS transceiver TX PLL or CDR can achieve lock to the reference clock. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 24.1. Download and install Patch 0.08 from the appropriate link below. Download patch 0.08 for Windows (quartus-24.1-0.08-windows.exe) Download patch 0.08 for Linux (quartus-24.1-0.08-linux.run) Download the Readme for patch 0.08 (quartus-24.1-0.08-readme.txt) This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3.
