Why does my EMIF IP RDIMM design have invalid assignments for SDA/SCL signals after compilation?
Description Due to a problem in the Quartus® Prime Pro Edition software versions 25.1.1, 25.3, and 25.3.1, the Fitter does not automatically place the I2C SDA/SCL signals when they are not explicitly assigned. Resolution To work around the problem, manually assign legal locations for the following signals on the AC1 lane: SDA: index 10 SCL: index 11 For details, see the “Address and Command Pin Placement” table in the External Memory Interfaces Agilex® 7 M‑Series FPGA IP User Guide (DDR5): Address and Command Pin Placement. Additional Information Affected Quartus® Prime versions: 25.1.1 25.3 25.3.1 This problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.
Why is the eCPRI FPGA IP unable to run on hardware using Stratix® 10 E-Tile with the Nios® V Processor for FPGA and turn on the interworking function (IWF)?
Description Due to a problem in the eCPRI FPGA IP version 3.0.2 in the example design, you may find that there is an error shown at the 10G transaction after changing the dynamic reconfiguration process from 25G to 10G. Resolution There is currently no plan to fix this behavior in a future Quartus® Prime release.Why does the o_rx_pcs_ready signal fail to assert in hardware for the PAM4 variant of the F-Tile Ethernet FPGA Hard IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.3 and earlier, the o_rx_pcs_ready signal will fail to assert in hardware for the PAM4 variant of the F-Tile Ethernet FPGA Hard IP when the variant is using both a 312.5MHz PMA reference clock and the Quartus Setting File(QSF) assignment VSR_MODE_LOW_LOSS is being used. Resolution To work around this problem, disable the QSF assignment VSR_MODE_LOW_LOSS. The problem has been fixed starting with Quartus® Prime Pro Edition software version 23.4.Why does the o_rx_pcs_ready signal fail to assert in hardware for the PAM4 variant of the F-Tile Ethernet Multirate FPGA IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.3 and earlier, the o_rx_pcs_ready signal will fail to assert in hardware for the PAM4 variant of the F-Tile Ethernet Multirate FPGA IP when the variant is using both a 312.5MHz PMA reference clock and the Quartus Setting File(QSF) assignment VSR_MODE_LOW_LOSS is being used. Resolution To work around this problem, disable the QSF assignment VSR_MODE_LOW_LOSS. The problem has been fixed starting with Quartus® Prime Pro Edition software version 23.4.Why are Toolkit instances (ETK, TTK) not detected for Agilex® 7 F-Tile Ethernet Hard IP in System-console after device configuration?
Description In designs using multiple instances of the Agilex® 7 F-Tile Ethernet Hard IP with Toolkit support enabled (ETK and TTK), the Toolkit instances may sometimes not be detected in the System Console GUI after programming the FPGA with the design .sof file. This behavior is caused by a problem in the F-Tile Ethernet Hard IP configuration. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 25.3.1. Download and apply attached patch 1.32, which restores Toolkit visibility in the System Console GUI for the F-Tile Ethernet Hard IP. This problem is scheduled to be fixed in a future release of Quartus Prime Pro Edition software.Why does EMIF for HPS LPDDR4 fail calibration on the Agilex® 5 FPGA and SoC FPGA?
Description In the Quartus® Prime Pro Edition Software 24.3, when configuring the Agilex® 5 FPGAs and SoC FPGAs with the EMIF for HPS IP and LPDDR4 device implemented as dual rank (2 chip selects), dual channels (i.e., 4 dies each being 16 Gbit in density), calibration can fail. Resolution This issue is fixed in 24.3.1 Quartus® Prime Pro Edition Software release. quartus-24.3-0.11-windows.exe quartus-24.3-0.11-linux.run quartus-24.3-0.11-readme.txtWhy do I see a simulation failure with the F-Tile Multi Channel DMA IP for PCI Express* Design Example using the Quartus® Prime Pro Edition Software version 26.1?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1, you may encounter simulation errors with the F-Tile Multi Channel DMA IP for PCI Express* Design Example. Synopsys VCS/VCS-MX : Error-[SE] Syntax error Following verilog source has syntax error : "./../..//pcie_ed_sim_tb.v", 2015: token is ')'... Error-[TMENF-IL] Top Module/Entity not found Top module/entity/config "pcie_ed_sim_tb.pcie_ed_sim_tb" is not found in library "PCIE_ED_SIM_TB". Error-[NM] No modules defined No modules defined in current design file(s). Siemens QuestaSim: ** Error: /mentor/questasim/2025.3/linux64/linux_x86_64/qrun failed. Error in macro ./run_msim_setup.tcl line 52 Cadence Xcelium: xmelab: *E,NOUNIT: Unable to find a unit named 'pcie_ed_sim_tb.pcie_ed_sim_tb' in the libraries. xmsim: *F,NOSNAP: Snapshot 'pcie_ed_sim_tb.pcie_ed_sim_tb' does not exist in the libraries. Aldec Riviera-Pro: Error: VCP2000 .../pcie_ed_sim_tb/pcie_ed_sim_tb/sim/pcie_ed_sim_tb.v : (1951, 6): Syntax error. Unexpected token: ). This problem is attributed to a limitation in the provided simulation testbench within this software release. It is important to note that this behavior is confined to the simulation environment and does not impact the functionality or performance of the design on hardware. Resolution This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.
Why does the example design fail to generate when "Dual Simplex Applied on JESD204B PHY" is selected with "Enable Manual F" enabled and the F value greater than 4?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1, you may observe the Dual Simplex (DS) PHY wrapper example design for GTS JESD204B IP fails to generate when the JESD204B DS Wrapper option is used with "Dual Simplex applied on JESD204B PHY" selected in the IP GUI, "Enable Manual F" is enabled, and the F value is set greater than 4. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition version 25.3.1.Why do the Resource Utilization results remain the same for the Agilex® 3 GTS JESD204B IP Core with either ECC_EN On or Off?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1, you may observe the resource utilization results remain the same in Agilex® 3 GTS JESD204B IP core with either ECC_EN On or Off Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition version 25.1.1.Why does the maximum observed channel-to-channel skew exceed 2 UI + 125 ps in an E-Tile transceiver under NRZ mode, even when TX PMA bonding is enabled?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, you may observe channel-to-channel skew exceeds 2 UI + 125 ps in E-Tile transceivers under NRZ mode even when TX PMA bonding is enabled. Resolution There is no workaround currently, and there is no plan to fix this problem.