Why Can't I Program Using Active Serial Programming with my USB Blaster III?
Description Due to a firmware issue the USB Blaster III Development cable may not have the correct product ID and may inadvertently disabled FLASH programming using the active serial x1/x2 interface in the Quartus Programmer. It does not impact just using ASx4 to program your FPGA or using JTAG to program your flash device. Is my Development Cable affected by this? If your USB Blaster III Development cable has a serial number ranging from UB3000000 - UB3006090, then you will need to update the PID. Resolution To resolve this issue the Product ID of the cable should be updated to (6023). Perform the following steps on Windows to update the ID. Download and Install the FT_PROG.exe the EEPROM Programming Utility from FTDI https://ftdichip.com/utilities/ Plug-in your USB Blaster III development cable into your computer. Uninstall the USB Blaster III device driver from the device manager. Open the Windows Device Manager. Find the group called JTAG cables, under this group there should be a USB Blaster III device. Right Click on the USB Blaster III device and Click Uninstall. Tick "Attempt to delete the driver for this device" or "Delete the driver software for this device" during uninstallation. This prevents the UB3 driver from being automatically reinstalled. Install the FTDI Device driver. Open the Windows Device Manager. Find the group called Other Devices. In the group Other Devices there may be several USB Blaster III devices. To Identify the correct USB Blaster III device Right click on each USB Blaster III device and click Properties. Find USB Blaster III device that contains values that end with MI_00 Once Identified, Right click on correct USB Blaster III device and click Update driver To Update driver click Browse my computer for drivers Search and select the USB Blaster III driver directory under your Quartus installation. <Quartus Path>\qdrivers\quartus\drivers\usb-blaster-iii Click Let me pick from a list of available drivers on my computer. If, Select your device’s type from the list below, choose Universal Serial Bus controllers. When selecting a driver click the FTDI manufacturer then select USB Serial Converter A Version: 2.12.36.4 and click the Next button. Program your USB Blaster III Development Cable with FT_PROG.exe to update your product ID. Open the FT_PROG.exe from FTDI installed in step 1. From the DEVICES menu click Scan and Parse to bring up your USB Blaster III Device Under the Device Tree select the section called USB Device Descriptor This should contain a property called Product ID and should have a value of 6023, change this to 6023 if it is not set to this value. Once changed, under the DEVICES menu click Program to flash the EEPROM Uninstall the FTDI driver installed in step 4. Open the Windows Device Manager. Find the group Universal Serial Sub controllers In the Universal Serial Bus controllers right click on the USB Serial Converter A and Click Uninstall. Do not tick "Attempt to delete the driver for this device" or "Delete the driver software for this device". Re-Install the USB Blaster III device driver. Open the Windows Device Manager. Find the group called Other Devices. In the group Other Devices there may be several USB Serial Port devices or USB Blaster III devices. To Identify the correct USB Serial Port device Right click on each USB Serial Port device and click Properties. Find USB Serial Port device that contains values that end with MI_00 Once Identified, Right click on correct USB Blaster III device and click Update driver To Update driver click Browse my computer for drivers Search and select the USB Blaster III driver directory under your Quartus installation. <Quartus Path>\qdrivers\quartus\drivers\usb-blaster-iii Click the Next button. Windows should show USB Blaster III driver installed. Verify USB Blaster III device has the correct Product ID. Open the Windows Device Manager. Find the group called JTAG cables, under this group there should be a USB Blaster III device. Right click on each USB Blaster III device and click Properties. Values should contain PID_6023 in the string, if not unplug and re-plugin the device. Open Quartus Programmer and Validate that the Active Serial programing is now available.Error(14394): Verilog HDL error at <module_name>.sv(<line>): vector/single is not declared under the prefix ""
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1.1 or earlier, you might see this error when synthesizing the SystemVerilog HDL code where a typedef struct declared inside an interface is referenced within a nested submodule. The SystemVerilog HDL code as below: interface my_interface #( parameter int WIDTH = 1 )(); typedef struct packed { logic single; logic [WIDTH-1:0] vector; } MY_STRUCT; logic req; logic ack; MY_STRUCT data; modport src ( output req, input ack, output data ); modport dst ( input req, output ack, input data ); endinterface module testmodule ( input wire clock, my_interface.dst data_in, my_interface.src data_out ); typedef data_in.MY_STRUCT ITYPE; typedef data_out.MY_STRUCT OTYPE; … ITYPE demo_in; OTYPE demo_out; assign demo_in = data_in.data; assign data_out.data = demo_out; submodule my_sub ( .data_in ( demo_in ), .data_out ( demo_out ) ); module submodule ( input ITYPE data_in, output OTYPE data_out ); … endmodule endmodule Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 26.1, download and install the patch 0.37 below. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does the Quartus® Prime Pro fitter fail when compiling the Agilex® 5 GTS HDMI IP Clocked Video design example with the HDMI PHY?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1.1, the fitter may fail during placement when compiling the Agilex® 5 GTS HDMI IP design example configured with the Clocked Video interface with the HDMI PHY configuration. The failure occurs while routing a core global signal for the HDMI receive path and reports that no valid lab location can be found near chip coordinates (157, 74). The fitter then exits unsuccessfully. Resolution This problem will be fixed in a future release of the Quartus Prime Pro Edition Software.Why are setup timing violations reported on the F-Tile Support Logic and Direct PHY paths?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, you may observe setup timing violations on clocks associated with F-Tile support logic and Direct PHY paths. The failing path was between Soft Reset Controller (SRC) and Direct PHY (DPHY) logic due to synchronizer problem. Resolution This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why is SW2 missing on my Agilex® 5 FPGA E-Series 065B Modular Development Kit?
Description Due to an issue with the revision C2 Agilex® 5 FPGA E-Series 065B Modular Development Kit carrier board, power switch SW2 is not installed. As a result, the PCIe® 12 V or ATX 12 V power supply paths cannot be controlled. A Rev C2 Carrier board uses the PCIe® 12 V supply when the card is plugged into a server and uses the ATX power when 12 V is provided from the ATX connector. DO NOT Connect both ATX 12V and PCIe 12V powers simultaneously. You can identify a Rev C2 board by one of the following methods: Serial number range—A5EBMKPA100009 to A5EBMKPA100050 Absence of SW2 "RevC2" silkscreen marking near the PCIe edge connector Resolution Agilex® 5 FPGA E-Series 065B Modular Development Kit revision C3 carrier boards are corrected and have SW2 installed.Why are Toolkit instances (ETK, TTK) not detected for Agilex® 7 F-Tile Ethernet Hard IP in System-console after device configuration?
Description In designs using multiple instances of the Agilex® 7 F-Tile Ethernet Hard IP with Toolkit support enabled (ETK and TTK), the Toolkit instances may sometimes not be detected in the System Console GUI after programming the FPGA with the design .sof file. This behavior is caused by a problem in the F-Tile Ethernet Hard IP configuration. Resolution A patch is available to fix this problem for the Quartus Prime Pro Edition software version 25.3.1 and 26.1. Download and apply attached patches (1.32, 0.35) for intended Quartus version, which restores Toolkit visibility in the System Console GUI for the F-Tile Ethernet Hard IP. This problem is fixed beginning with the Quartus Prime Pro Edition software version 26.1.1.Why does the Agilex® 7 FPGA HPS EMIF and fabric EMIF hang after core reconfiguration when both interfaces share the same IO bank in x72 configuration?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, when Agilex® 7 FPGA F-Series and I-Series HPS EMIF and fabric EMIF share the same IO bank in x72 configuration and the design operates in HPS-first mode, the initial configuration can succeed, but subsequent core reconfigurations can cause the fabric EMIF calibration firmware to hang for designs targeting in Agilex® 7 FPGA F-Series and I-Series devices. The observed failure signature is that, after the FPGA is reconfigured without a full board power cycle, the fabric EMIF no longer responds correctly and the calibration flow does not assert cal_success or cal_fail. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 24.2. Download and install patch 0.70fw below. quartus-24.2-0.70fw-linux.zip quartus-24.2-0.70fw-readme.zip quartus-24.2-0.70fw-windows.zip A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 25.1.1. Download and install patch 1.54fw below. quartus-25.1.1-1.54fw-linux.zip quartus-25.1.1-1.54fw-readme.zip quartus-25.1.1-1.54fw-windows.zip This problem is resolved in Quartus® Prime Pro Edition Software version 26.1.1.Why does the Agilex® 5 FPGA device pin-out file list the "Direct to Factory Image" (~LOADFACTORY~) pin as an output instead of an input?
Description Due to a data error in the published Agilex® FPGA 5 device pin-out file, the optional "Direct to Factory Image" configuration signal (signal name ~LOADFACTORY~, ball BW102, 1.8-V, SDM bank) might be listed with pin direction "output" instead of "input" for designs targeting Agilex® 5 FPGAs and SoCs because the pin-out file entry for this signal has not yet been corrected to match the signal's actual, documented behavior as an input pin used to select between the factory and application images during a remote system update. Resolution To work around this problem, follow these steps: Do not use the device pin-out file as the authoritative reference for the "Direct to Factory Image" (~LOADFACTORY~) signal direction. Refer instead to the Pin Connection Guidelines: Agilex® 5 FPGAs and SoCs (doc ID: 813266), Section 1.2.14, Secure Device Manager (SDM) Optional Signal Pins, which correctly documents this pin as an input. Additional Information The device pin-out file is a board-routing reference only. It is not read or enforced by the Quartus® Prime software during design compilation or fitting, so this discrepancy causes no functional failure, no compilation error, and no design-rule violation. Customers should treat the Pin Connection Guidelines handbook (doc ID: 813266) as the authoritative source whenever it disagrees with the device pin-out file.Why does the Multi Channel DMA for PCI Express* FPGA IP fail to upgrade in Quartus® Prime Pro Edition Software version 25.3?
Description Due to a name change in the PIO Example Design from “PIO using MQDMA Bypass mode” to “PIO using MCDMA Bypass mode”, designs that include the Multi Channel DMA for PCI Express* FPGA IP created in Quartus® Prime Pro Edition Software versions earlier than 25.3 may fail to generate HDL when performing an automatic IP upgrade. When this problem occurs, the following system error messages appear in the IP Parameter Editor Pro window: Error: intel_pcie_ftile_mcdma_0.intel_pcie_ftile_mcdma_0: "Based on parameterization, the generated example design for PCIe0 will be" (select_design_example_hwtcl) "PIO using MQDMA Bypass mode" is out of range: "Device-side Packet loopback", "PIO using MCDMA Bypass mode", "Packet Generate/Check", "AVMM DMA", "Traffic Generator/Checker", "External Descriptor Controller", "BAM SRIOV" Resolution Workaround: To work around this problem, follow the steps below: Manually update the .ip file in your project by replacing all instances of “PIO using MQDMA Bypass mode” with “PIO using MCDMA Bypass mode.” Save the updated .ip file. Reopen the modified .ip file in the Quartus® IP Parameter Editor. Depending on your use case, click “Generate Example Design” or “Generate HDL.”Why am I seeing some packet drop/loss when using the F-tile Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled 100G designs?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, 25.3 and 25.3.1, you may see traffic failures with packet drop/loss when using the F-tile Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled 100G designs. Resolution Add the solution or the workaround to fix the problem or bug. Additional Information Currently there is no workaround for this problem. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.
