number_7
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Re: Agilex 7 i series serdes capability
Hi AR_A_Intel, Thanks for considering my query and response. I am working on transceiver IP design to check the Serdes capability. Link for board files referring this link for target device part number agib027r31b1e1vaa, to get the board files under Table 3. Documentation in installer package but could not find a link for this particular device -DK-SI-AGI027FB, i have doubt like whether i am referring the correct link can you help on this to get the board files so that i can get the better understanding on available configurations. Regarding reference eye diagrams still i didnt get that, so, if possible, can you provide any source to get the eye diagram to have an idea on Data rate range for FGT PMA's which is mentioned as 1-32 Gbps NRZ 20-58.125 PAM4DisplayPort IP quartus v24.1 reference design with ftile transceiver IP
I have generated the reference design for display port IP with help of user guide " F-Tile DisplayPort Intel® FPGA IP Design Example User Guide" version 20.0.1. The reference design having F tile PMA/FEC Direct Phy Intel FPGA IP. on analyzing the reference design IP instance file the interface port signals are different from the interface signals for the same IP from the IP catalog. does the reference design using any other customized transceiver IP which is not listed in IP catalog?dynamic reconfiguration transceiver Agilex7 IP
I want to use the tranceiver IP for my design which should dynamically reconfigure for different data rates. F tile direct phy IP is totally different when compared to A10. on user guide i found that for dynamic reconfiguration we have to use multirate IP by adding different profiles. My dout is can we do the DR with Ftile direct PHY IP or only we have to use multirate IP.Re: Reference design F tile PHY IP
Hi @ventt I have attached the IP for your reference. IP upgrade component window showing F tile tx version 4.4. Device Agilex 7 I- series, tool version 24.1 and it will support F-tile IP 4.8. please correct me if i did any wrong configuration while creating example design.Reference design F tile PHY IP
I have created the example design for Display port Tx only using Quartus prime pro 24.1 in that F tile Phy IP version showing version mismtach as the design using 4.4 and the tool having version 4.8. At this stage i couldnt find the PHY configuration used for that example design.Arria10 Transceiver IP critical warning
While using tranceiver IP A10 i have chosen number of data channel us 4 but during implementation i got critical warning as " 32 unused data channel in RX and 32 unused data channel in TX. Added below assignment in .qsf with reference to Intel link but still not fixed set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
