DisplayPort IP quartus v24.1 reference design with ftile transceiver IP

Hi @number_7,

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. As a result, we have a backlog of cases that we are currently working through.

Please be assured that we are doing everything we can to resolve this as quickly as possible. This will take some time, and we appreciate your patience and understanding during this period of time. Your case will be attended to by AE soonest possible.

Thank you again for your patience and understanding, and we are committed to provide you with the best possible support.

Best Regards,

Ven

Hi @number_7,

No, it is not a customized transceiver IP. The design example uses the F-Tile PMA/FEC Direct PHY Intel FPGA IP, which you can find in the IP Catalog.

For more information about the F-Tile PMA/FEC Direct PHY Intel FPGA IP, please refer to the User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683872/24-2-4-9-0/f-tile-overview.html

Thanks.

Best Regards,

Ven

Hi @number_7,

Good day.

May I know if you have any further inquiries regarding this forum thread?

Thanks.

Best Regards,

Ven

Hi @number_7,

As there are no further inquiries, I will transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desired request, and post a feed/response within the next 15 days to allow me to continue to support you.

After 15 days, this thread will be transitioned to community support.

The community users will be able to help you with your follow-up questions.

We apologize for the inconvenience caused and thank you for your understanding.

Thanks.

Best Regards,

Ven