shivajim
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Re: Error when programming Agilex
Hello, It seems I have a similar problem, sdm looks stucking while accessing dcdc+power management chip with slave address 0x47 while re-programming sof, i saw in devkit schematics ltc3888 is configured with slave address 0x47. The kit user guide asking to set the pwrmgt parameters (0x47, slave deivce type - others etc). i've tried setting other devices even but no luck. I able to program *.sof for the first time after a power cycle, then same *.sof re-programming fails with the following error. To program sof again I have to powercycle! Error(18948): Error message received from device: External hardware access error. (Subcode 0xC80E, Info 0x00000047, Location 0x00001800) it looks due to some reason smbus hung in an unrecoverable state after first time sof program, not allowing sdm to access again? needs to be powercycled.. please help how to fix this! devkit: DK-DEV-AGI027RBES Thanks, Shivaji Mr-tile pipe direct emib deskew
Hello Intel, The r-tile user guide for pipe direct mode says on deskew that user application logic should toggle txdeskewmarker_i, but it looks not clear. Can someone tell me when this signal toggle after reset / afterr-tile start generating the *_tx_clk_out_o ? what data to be sent on *_txdata? Every 16 cycles - means 1 pulse cycle where some data is to be transferred on *_txdata and wait for *_dsk_valid_0, if not then second pulse should be sent and so on, what should be done? Is this not required for rx?Agilex Clock Primitives (Mux/Dividers on Clock Network)
Hello, Are their any primitives like bufgmux, bufgdiv in altera/agilex FPGA which help user to add mux or dividers to the clock network instead of fabric resources? If yes what are those, and how to constraints them? it's very hard in netlist veiwer to copy the net/port/pin name as this is easily possible in xilinx tools. what are best ways to constraints clock muxes which are added to clocks paths from pll output or phy generated clocks. The intelclkctrl ip I've added now looks like it's inferring combinatorial logic and messing up the timing! Thanks, Shivaji Mr-tile pipe direct mode gen3 rxeq
Hello, I'm simulating r-tile at gen3 speeds using a soft PCIe controller in fpga fabric. The controller is enabling rxeqeval at recovery phase2 over m2p and r-tile acknowledged on p2m message bus (see below image) saying message command is accepted. It looks like r-tile is doing anyting ie. no fom values at ep side, i gave a very long run! Can you help me understand how to perform equalization in pipe direct mode at gen3/4/5 speed? r-tile says it only supports fom, what is expectation, please provide message bus transaction/behaviour? also, i saw that r-tile always providing the fs/lf values, and for any coefficients request it gives blank reponse. Thanks, Shivaji MAgilex7i - tennm_hps_hps & tennm_hps_mpfe design units are unresolved
Hello, I am trying to do gate level simulation of "AGIB027R29A1E2VR3" having HPS in the project with xcelium. The elaborator unable to resolve 10nm hps instances, can anyone help me which are libraries other than "tennm_ver" are needed to compile ? snipet: Thanks, Shivaji Mquartus prime pro 24.1 simple_dual_port_ram addresstall tied to 1 in netlist
Hi, I am using "simple_dual_port_ram" primitive in my design having for agilex 7i (part#AGIB027R29A1E2VR3), I am forcing the addressstall_a/b signals to zero in the instance, the design is being compiled using quartus prime pro 24.1. I see these pins in the netlist are being tied to 1. Can you help me why this is happening? instantiation: Netlist: Thanks, Shivaji M
