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shivajim's avatar
shivajim
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1 year ago

Agilex Clock Primitives (Mux/Dividers on Clock Network)

Hello,

Are their any primitives like bufgmux, bufgdiv in altera/agilex FPGA which help user to add mux or dividers to the clock network instead of fabric resources? If yes what are those, and how to constraints them? it's very hard in netlist veiwer to copy the net/port/pin name as this is easily possible in xilinx tools. what are best ways to constraints clock muxes which are added to clocks paths from pll output or phy generated clocks.

The intelclkctrl ip I've added now looks like it's inferring combinatorial logic and messing up the timing!

Thanks,

Shivaji M

Configuration
Fpga Devkit

5 Replies

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,


    May I know if the issue has been resolved and if you still need help with this case?


    Regards,

    Richard Tan


    • shivajim's avatar
      shivajim
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hi Richard,

      No, are you available for call?

      Thanks,

      Shivaji M

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    No, I don't think we have corresponding primitives like Xilinx's primitives. Instead, we have the Clock Control IP for clock management.

    The only user guide with information on primitives that we have is the Designing with Low-Level Primitives User Guide. You can download it here:

    https://cdrdv2-public.intel.com/654838/ug_low_level.pdf

    (Clicking the link will auto-download the UG.)

    Kindly share your design by archiving the project (Project > Archive Project) so I can investigate the issue you're facing with the Clock Control IP.

    Additionally, we sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. As a result, we have a backlog of cases that we are currently working through.

    Please be assured that we are doing everything we can to resolve this as quickly as possible. This will take some time, and we appreciate your patience and understanding during this period of time. Your case will be attended by AE soonest possible.

    Thank you again for your patience and understanding, and we are committed to provide you with the best possible support.

    Regards,

    Richard Tan

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Any update on this?

    Do you able to share the design with us?


    Regards,

    Richard Tan


  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

    If you have any further questions or concerns, please don't hesitate to reach out. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

    The community users will be able to help you on your follow-up questions.

    Thank you for reaching out to us!

    Best Regards,

    Richard Tan