Forum Discussion

shivajim's avatar
shivajim
Icon for New Contributor rankNew Contributor
1 year ago

Agilex Clock Primitives (Mux/Dividers on Clock Network)

Hello, Are their any primitives like bufgmux, bufgdiv in altera/agilex FPGA which help user to add mux or dividers to the clock network instead of fabric resources? If yes what are those, and how to...
Configuration
Fpga Devkit
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

No, I don't think we have corresponding primitives like Xilinx's primitives. Instead, we have the Clock Control IP for clock management.

The only user guide with information on primitives that we have is the Designing with Low-Level Primitives User Guide. You can download it here:

https://cdrdv2-public.intel.com/654838/ug_low_level.pdf

(Clicking the link will auto-download the UG.)

Kindly share your design by archiving the project (Project > Archive Project) so I can investigate the issue you're facing with the Clock Control IP.

Additionally, we sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. As a result, we have a backlog of cases that we are currently working through.

Please be assured that we are doing everything we can to resolve this as quickly as possible. This will take some time, and we appreciate your patience and understanding during this period of time. Your case will be attended by AE soonest possible.

Thank you again for your patience and understanding, and we are committed to provide you with the best possible support.

Regards,

Richard Tan