r-tile pipe direct emib deskew

Hello Intel,

The r-tile user guide for pipe direct mode says on deskew that user application logic should toggle txdeskewmarker_i, but it looks not clear. Can someone tell me when this signal toggle after reset / afterr-tile start generating the *_tx_clk_out_o ? what data to be sent on *_txdata?

Every 16 cycles - means 1 pulse cycle where some data is to be transferred on *_txdata and wait for *_dsk_valid_0, if not then second pulse should be sent and so on, what should be done?

Is this not required for rx?