quartus prime pro 24.1 simple_dual_port_ram addresstall tied to 1 in netlist

Hi,

I am using "simple_dual_port_ram" primitive in my design having for agilex 7i (part#AGIB027R29A1E2VR3), I am forcing the addressstall_a/b signals to zero in the instance, the design is being compiled using quartus prime pro 24.1. I see these pins in the netlist are being tied to 1. Can you help me why this is happening?

instantiation:

Netlist:

Thanks,

Shivaji M