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shivajim's avatar
shivajim
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2 years ago

quartus prime pro 24.1 simple_dual_port_ram addresstall tied to 1 in netlist

Hi, I am using "simple_dual_port_ram" primitive in my design having for agilex 7i (part#AGIB027R29A1E2VR3), I am forcing the addressstall_a/b signals to zero in the instance, the design is being com...
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felix_zhu's avatar
felix_zhu
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2 years ago

Hi,

Can you share the project .qar to me? And did you see any warning message or tie the address to a instant value?


Felix Zhu