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shivajim's avatar
shivajim
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1 year ago

r-tile pipe direct mode gen3 rxeq

Hello,

I'm simulating r-tile at gen3 speeds using a soft PCIe controller in fpga fabric. The controller is enabling rxeqeval at recovery phase2 over m2p and r-tile acknowledged on p2m message bus (see below image) saying message command is accepted. It looks like r-tile is doing anyting ie. no fom values at ep side, i gave a very long run! Can you help me understand how to perform equalization in pipe direct mode at gen3/4/5 speed? r-tile says it only supports fom, what is expectation, please provide message bus transaction/behaviour?

also, i saw that r-tile always providing the fs/lf values, and for any coefficients request it gives blank reponse.

Thanks,

Shivaji M

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6 Replies

  • shivajim's avatar
    shivajim
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hello,

    Is their way i can directly reachout intel AE on this? please comment if anyone knows!

    Thanks,

    Shivaji M

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi @shivajim,


    We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. As a result, we have a backlog of cases that we are currently working through.


    Please be assured that we are doing everything we can to resolve this as quickly as possible. This will take some time, and we appreciate your patience and understanding during this period of time. Your case will be attended to by AE soonest possible.


    Thank you again for your patience and understanding, and we are committed to provide you with the best possible support.


    Best Regards,

    Ven


  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi shivajim,


    Please refer to Section 4.2.3 "Link Equalization Procedure for 8.0 GT/s and Higher Data Rates" in the PCI Express Base Specification Revision 5.0 for detailed information on the equalization procedures at Gen3/4/5 speeds.


    The message bus signals are used for PHY (P)-MAC (M) communication. They reduce the number of dedicated signals for implementations like link equalization, lane margining etc.

    https://www.intel.com/content/www/us/en/docs/programmable/683501/24-2-11-3-0/message-bus-signals.html


    Thanks.

    Best Regards,

    Ven


  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi shivajim,


    Good day.

    May I know if you have any further inquiries regarding this forum thread?


    Thanks.

    Best Regards,

    Ven


  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi shivajim,


    As there are no further inquiries, I will transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desired request, and post a feed/response within the next 15 days to allow me to continue to support you.


    After 15 days, this thread will be transitioned to community support.

    The community users will be able to help you with your follow-up questions.


    We apologize for the inconvenience caused and thank you for your understanding.


    Thanks.

    Best Regards,

    Ven