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shivajim's avatar
shivajim
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1 year ago

r-tile pipe direct mode gen3 rxeq

Hello, I'm simulating r-tile at gen3 speeds using a soft PCIe controller in fpga fabric. The controller is enabling rxeqeval at recovery phase2 over m2p and r-tile acknowledged on p2m message bus (s...
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VenT_Altera's avatar
VenT_Altera
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1 year ago

Hi shivajim,


Please refer to Section 4.2.3 "Link Equalization Procedure for 8.0 GT/s and Higher Data Rates" in the PCI Express Base Specification Revision 5.0 for detailed information on the equalization procedures at Gen3/4/5 speeds.


The message bus signals are used for PHY (P)-MAC (M) communication. They reduce the number of dedicated signals for implementations like link equalization, lane margining etc.

https://www.intel.com/content/www/us/en/docs/programmable/683501/24-2-11-3-0/message-bus-signals.html


Thanks.

Best Regards,

Ven