ALMSlinger
New ContributorJoined 3 years ago
User Profile
New Contributor
User Widgets
Contributions
Re: Signaltap on dut|altpcie_a10_hip_pipen1b|test_out[319:0]
Hi Wincent, According to this timing analyzer report, clocking signaltap with coreclkout will create clock transfers between test_out and signal tap nodes. The test_out is being clocked out by pld_clk. The problem is that signaltap complains that PLD_CLK is not running even after PCIe end point successful enumerates. Do we need to write any value on test_in bus to make the pld_clk run? The stp file is called pcie_dbg.stp in the zip file that I attached early on in the post. Let me know if you have trouble accessing it. Thank you. Best regards, SanjayRe: Signaltap on dut|altpcie_a10_hip_pipen1b|test_out[319:0]
Thanks Wincent for digging this out. I had seen this before. Unfortunately, the spreadsheet doesn't say which clock to use to sample test_out. I don't undersand what you mean by ignoring the test_out signal. I want to see what is on the following signals. So I am asking again - what clock should I use in signaltap to sample these signals? rxvalid0 1 test_out [86] test_out [246] rxblkst0 1 test_out [85] test_out [245] rxsynchd0 2 test_out [84:83] test_out [244:243] rxdataskip0 1 test_out [82] test_out [242] rxdatak0 4 test_out [81:78] test_out [241:238] rxdata0 32 test_out [77:46] test_out [237:206] powerdown0 2 test_out [45:44] test_out [205:204] rxpolarity0 1 test_out [43] test_out [203] txcompl0 1 test_out [42] test_out [202] txelecidle0 1 test_out [41] test_out [201] txdetectrx0 1 test_out [40] test_out [200] txblkst0 1 test_out [39] test_out [199] txsynchd0 2 test_out [38:37] test_out [198:197] txdataskip0 1 test_out [36] test_out [196] txdatak0 4 test_out [35:32] test_out [195:192] txdata0 32 test_out [31:0] test_out [191:160] Thank you for the help. Best regards, SanjayRe: Signaltap on dut|altpcie_a10_hip_pipen1b|test_out[319:0]
Wincent, The test_out signals are the pipe interface signals. I need to see what is coming out of the MAC/PCS sublayer. The test_out to coreclkout is across clock domains. You can see this from the timing analyzer report. Please see the picture. I do not have a picture of signaltap where it complained that the sampling clock was missing. But the screen shot of the signaltap screen is attached. Yes! LTSSM enters L0 state. I have attached the Arria 10 GX dev board example design project with this signal tap. Please check the attached zip file.Signaltap on dut|altpcie_a10_hip_pipen1b|test_out[319:0]
Hello, I am using pld_clk as signaltap clk to sample the test_out[319:0] signals of the pipe interface in Arria10GX HIP. But on the board the signaltap complains that pld_clk was not found. This happens even after the board enumerates successfully. How do capture test_out in signaltap? Thank you. Best regardsRe: Platform Designer - clock bridge : Interfaces must be on the same clock domain
They use common reset that is synchronous to the clock generated by the pll. The same clock that is input to the clock bridge. I even tried to add a parallel reset bridge which did the same thing as the clocks. But that doesn't help. I get the same error. Thank you. Best regards.Platform Designer - clock bridge : Interfaces must be on the same clock domain
Hi, To split up the a large clock tree, I inserted a clock bridge in my platform designer file. Now, I have one PLL generated clock CLK --> clk bridge --> cout_0, cout_1, cout_2. The clock bridge frequency is set to "0" so "derived" from what I can see. Previously, I had CLK going to IP blocks - A,B,C. Now I have : cout_0 --> A, cout_1 --> B, cout_2 --> C There are custom data busses that connect between A--> B --> C. Doing this throws a connectivity error. It says that A.databus and B.databus should be on the same clock domain. The "clock domains" tab in platform designer gui shows that all the modules are in the "CLK" clock domain. i.e. the input clock to the clock bridge. How can I fix this this error? Thank you. Best regards,Re: How to program application image address in flash with Arria 10GX RSU IP?
Thank you for trying. This doesn't answer the question though. I am asking when does RSU IP block update the image offset at location 0x10 in the flash so that next time the FPGA loads the configuration bitstream from that location. Register 3 specifies the address of the boot image. But writing to it doesn't update the flash. Thank you. Best regards.
