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ALMSlinger's avatar
ALMSlinger
Icon for New Contributor rankNew Contributor
1 year ago

Platform Designer - clock bridge : Interfaces must be on the same clock domain

Hi, To split up the a large clock tree, I inserted a clock bridge in my platform designer file. Now, I have one PLL generated clock CLK --> clk bridge --> cout_0, cout_1, cout_2. The clock bridge...
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ALMSlinger's avatar
ALMSlinger
Icon for New Contributor rankNew Contributor
1 year ago

They use common reset that is synchronous to the clock generated by the pll. The same clock that is input to the clock bridge. I even tried to add a parallel reset bridge which did the same thing as the clocks. But that doesn't help. I get the same error.

Thank you.

Best regards.

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Can you show screenshots of parameters and how you're connecting things?