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New ContributorPlatform Designer - clock bridge : Interfaces must be on the same clock domain
Hi,
To split up the a large clock tree, I inserted a clock bridge in my platform designer file.
Now, I have one PLL generated clock CLK --> clk bridge --> cout_0, cout_1, cout_2.
The clock bridge frequency is set to "0" so "derived" from what I can see.
Previously, I had CLK going to IP blocks - A,B,C.
Now I have :
cout_0 --> A,
cout_1 --> B,
cout_2 --> C
There are custom data busses that connect between A--> B --> C.
Doing this throws a connectivity error. It says that A.databus and B.databus should be on the same clock domain.
The "clock domains" tab in platform designer gui shows that all the modules are in the "CLK" clock domain. i.e. the input clock to the clock bridge.
How can I fix this this error?
Thank you.
Best regards,
6 Replies
SyafieqSSuper Contributor
Seem like to me the clock bridge you inserted is not properly synchronizing the clocks for the data buses A, B, and C, which is causing the connectivity error. To fix this, you need to ensure that the data buses are properly synchronized to the same clock domain.
sstrellWhat are A, B, and C using for reset? Perhaps the resets are synchronous to a different clock domain.
Screenshots would help.
ALMSlingerThey use common reset that is synchronous to the clock generated by the pll. The same clock that is input to the clock bridge. I even tried to add a parallel reset bridge which did the same thing as the clocks. But that doesn't help. I get the same error.
Thank you.
Best regards.
- sstrell
Can you show screenshots of parameters and how you're connecting things?
- SyafieqS
Any update from previous reply?
- SyafieqS
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