ALMSlinger
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New ContributorPlatform Designer - clock bridge : Interfaces must be on the same clock domain
Hi,
To split up the a large clock tree, I inserted a clock bridge in my platform designer file.
Now, I have one PLL generated clock CLK --> clk bridge --> cout_0, cout_1, cout_2.
The clock bridge frequency is set to "0" so "derived" from what I can see.
Previously, I had CLK going to IP blocks - A,B,C.
Now I have :
cout_0 --> A,
cout_1 --> B,
cout_2 --> C
There are custom data busses that connect between A--> B --> C.
Doing this throws a connectivity error. It says that A.databus and B.databus should be on the same clock domain.
The "clock domains" tab in platform designer gui shows that all the modules are in the "CLK" clock domain. i.e. the input clock to the clock bridge.
How can I fix this this error?
Thank you.
Best regards,
