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ALMSlinger
New Contributor
New ContributorPlatform Designer - clock bridge : Interfaces must be on the same clock domain
Hi, To split up the a large clock tree, I inserted a clock bridge in my platform designer file. Now, I have one PLL generated clock CLK --> clk bridge --> cout_0, cout_1, cout_2. The clock bridge...
sstrell
Super Contributor
Super ContributorWhat are A, B, and C using for reset? Perhaps the resets are synchronous to a different clock domain.
Screenshots would help.
