Forum Discussion
ALMSlinger
New Contributor
New ContributorPlatform Designer - clock bridge : Interfaces must be on the same clock domain
Hi, To split up the a large clock tree, I inserted a clock bridge in my platform designer file. Now, I have one PLL generated clock CLK --> clk bridge --> cout_0, cout_1, cout_2. The clock bridge...
SyafieqS
Super Contributor
Super ContributorSeem like to me the clock bridge you inserted is not properly synchronizing the clocks for the data buses A, B, and C, which is causing the connectivity error. To fix this, you need to ensure that the data buses are properly synchronized to the same clock domain.
