drivers/src/altera_s10_mailbox_client.c:32:59: error: 'OS_FLAG_SET' undeclared (first use in this function); did you mean 'ALT_FLAG_SET'?
Description Due to a problem in Quartus® Prime Pro Edition Software, you might see an error when compiling Nios® V software with the Mailbox Client IP or 16550 Compatible UART Core driver, in FreeRTOS environment. This is because the driver software of the IP is using “MicroC/OS-II”-specific OS_* macros. Resolution The recommended macros are the OS-independent ALT_* macros. MicroC/OS-II Real-Time Operating System - Thread-Safe HAL Drivers FreeRTOS Real-Time Operating System - Thread-Safe HAL Drivers Replace the OS_* accordingly. MicroC/OS-II Macros Replace to OS_FLAG_SET ALT_FLAG_SET OS_FLAG_CLEAR ALT_FLAG_CLEAR OS_FLAG_WAIT_SET_ALL ALT_FLAG_WAIT_SET_ALL_WO_CONSUME (OS_FLAG_WAIT_SET_ALL + OS_FLAG_CONSUME) ALT_FLAG_WAIT_SET_ALL_WITH_CONSUME OS_FLAG_WAIT_SET_ANY ALT_FLAG_WAIT_SET_ANY_WO_CONSUME (OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME) ALT_FLAG_WAIT_SET_ANY_WITH_CONSUME OS_FLAG_GRP* group ALT_FLAG_GRP(group)
Error: Internal Error: Sub-system: SIN, File: /quartus/tsm/sin/sin_micro_tnodes_utility.cpp, Line: 431 - Unknown I/O cell name: 'dibss'
Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.3, you may see this error due to unrecognised and unbypassed new pins added in Direct Interface Bus (DIB) IP Intel® pins for IO timing during compilation in Intel® Stratix®10 devices. Resolution A patch is available to workaround this problem for the Intel® Quartus® Prime Pro Edition software version 20.3. Download and install Patch 0.46pro from the appropriate link below. Download patch Intel® Quartus® Prime Pro Edition 20.3 Patch 0.46pro for Windows (.exe) Download patch Intel® Quartus® Prime Pro Edition 20.3 Patch 0.46pro for Linux (.run) Download the Readme for Intel® Quartus® Prime Pro Edition 20.3 Patch 0.46pro (.txt) This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 21.1Error: LVDS SDC cannot find IOPLL. Ensure IOPLL SDC is listed before LVDS SDC in qsf
Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.1, you may see this error message in projects that include the LVDS SERDES Intel® FPGA IP configured in External PLL Mode. The error may be seen even if the Quartus® Prime IP File (.qip) of the IOPLL Intel® FPGA IP is listed before the '.qip' file of the LVDS SERDES Intel® FPGA IP in the project Quartus® Prime Settings File (.qsf). Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Edition Pro software version 19.1 Download and install Patch 0.19 for the Intel® Quartus® Prime Edition Pro software version 19.1 from the appropriate link below (To download .run file, right-click on the above link and choose “Save link as”) Intel® Quartus® Prime Edition Pro software version 19.1 patch Download patch 0.19 for Windows (.exe) Download patch 0.19 for Linux (.run) Download the Readme for patch 0.19 (.txt) This problem is fixed starting with in the Intel® Quartus® Prime Pro Edition software version 19.2.Why does the Intel® Stratix® 10 FPGA fail to configure when programing a .jic file?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 21.1, an invalid .jic file will be generated when incompatible frequencies are used for ACTIVE_SERIAL_CLOCK and DEVICE_INITIALIZATION_CLOCK in your Quartus Settings File (.qsf). The configuration flow will fail using this .jic file. Resolution To avoid this error, make sure your .qsf file has a compatible set of frequencies for ACTIVE_SERIAL_CLOCK and DEVICE_INITIALIZATION_CLOCK. The valid AS_CLK settings can be found in the Intel® Stratix® 10 Configuration User Guide. A patch is available to check for valid frequencies for ACTIVE_SERIAL_CLOCK and DEVICE_INITIALIZATION_CLOCK in the Quartus Settings File (.qsf). Download and install Patch 0.06 from the appropriate link below. > Download patch Intel® Quartus® Prime Pro Edition 21.1 Patch 0.06 for Windows (.exe) > Download patch Intel® Quartus® Prime Pro Edition 21.1 Patch 0.06 for Linux (.run) > Download the Readme for Intel® Quartus® Prime Pro Edition 21.1 Patch 0.06 (.txt) After installing patch 0.06, in your next compilation with an incompatible set of frequencies you will get an error message during the Assembler stage saying "The active serial clock is not supported in device initialization clock" This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.2.
Why does Board Support Package (BSP) Editor in Quartus® Prime Pro Embedded Edition fails to generate Nios® V processor BSP project from .vds file?
Description Due to a problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, the BSP Editor fails to generate Nios® V processor BSP project from .vds file. This issue is not affecting BSP project generation: From .qsys file using BSP Editor in Quartus® Prime Pro Embedded Edition software, or Using BSP Editor in Quartus® Prime Pro Edition software. This issue is caused by a software bug in the BSP Editor of Quartus® Prime Pro Embedded Edition software. Refer to Nios V Embedded Processor Design Handbook - Recommended Tools from Quartus Prime Installer (PDF) for more information on the difference between Quartus® Prime Pro Edition and Quartus® Prime Pro Embedded Edition software. Resolution To work around this problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, apply either one of the workarounds below: Switch from .vds to .qsys file Use BSP Editor in Quartus® Prime Pro Edition software version 26.1 or 26.1.1 This problem is currently scheduled to be resolved in a future release of the Quartus® Prime Pro Embedded Edition Software.Is the Intel® Stratix® 10 timing model correct in the Intel® Quartus® Prime Pro Edition software versions 18.0 Update 1 and 18.1?
Description No, the Intel® Stratix® 10 timing model in the Intel® Quartus® Prime Pro Edition software version 18.0 Update 1 and 18.1 has a small miscorrelation. This is corrected in the Intel Quartus Prime Pro Edition software version 18.1 Update 1. These design scenarios may be affected: Designs that use source synchronous clocking Designs with transfers between the reference clock and the output clock for IOPLLs Designs with transfers between output clocks from different IOPLLs with different reference clocks Almost all designs will see timing delays change but most transfers will be unaffected because of either Common Clock Pessimism Removal (CCPR) or the transfer being asynchronous. Resolution All Intel Stratix 10 designs should be reanalyzed for timing in the Intel Quartus Prime Pro Edition software version 18.1 Update 1 or a patched version of 18.0 Update 1 or 18.1. Download and install Patch 1.45 for 18.0 Update 1 from the appropriate link below. Download the version 18.0 Update 1 patch 1.45 for Windows (.exe) Download the version 18.0 Update 1 patch 1.45 for Linux (.run) Download the Readme for the Intel Quartus Prime Pro edition software version 18.0 Update 1 patch 1.45 (.txt) Download and install Patch 0.31 for 18.1 from the appropriate link below. Download the version 18.1 patch 0.31 for Windows (.exe) Download the version 18.1 patch 0.31 for Linux (.run) Download the Readme for the Intel Quartus Prime Pro edition software version 18.1 patch 0.31 (.txt) For designs that are already in production: 1. Download and run the script lut8_iobuf_qsh_v3.tcl to check if the compiled design is affected by this problem. Command -> quartus_sh -t lut8_iobuf_qsh_v3.tcl -project <project name> -revision <revision name> -npaths 100 -debug 0 -verbose -check_lutmasks -vo_file simulation/modelsim/<revision name>.vo Output -> lut8check.rpt, iobuf.rpt, paths.csv iobuf.rpt and paths.csv report the paths that are affected by the timing model change 2. If there are no paths identified as impacted, no action is needed. 3. If there are paths identified as impacted and using the Intel Quartus Prime Pro Edition software version 18.1 or earlier, rerun timing analysis using the patched version of the Intel Quartus Prime Pro Edition software version 18.0 Update 1 or 18.1 a. If there is not sufficient margin then recompile the design. b. If there is sufficient margin, you may choose to perform no action Steps to rerun timing analysis: 1. Download and install patch 1.45 for 18.0.1 or patch 0.31 for 18.1 2. Open the design using the patched version of the Intel Quartus Prime Pro Edition software 3. Go to Tools -> Timing Analyzer and open Timing Analyzer. 4. Run the following commands: a. create_timing_netlist -model slow -force_dat b. read_sdc c. update_timing_netlist lut8check.rpt reports the LUTs impacted by the problem described in KDB Why do I have functional errors in my Intel® Stratix® 10 design? If this report contains "Found 0 LUTs with potentially incorrect bit settings" then the compiled design is safe. If the design is affected then the LUTs with this problem will be listed in the report.Why isn’t there any PLLs usage if I compile the project with the Stratix® 10 FPGA E-tile transceiver channels ?
Description This is an expected behaviour. You will see "Total PLLs" usage is 0 if you only instantiate Intel® Stratix® 10 FPGA E-tile transceiver channels in the design. The Stratix® 10 FPGA E-tile transceiver channel phase-locked loop (PLL) would not be counted in the total PLLs summary. For example, if you use Stratix® 10 device 1ST280EY2F55, and instantiate four E-tile transceiver channels. After compilation, you will still see the “Total PLLs 0/64(0%)” in the flow summary of the compilation report. Resolution All PLLs shown in the compilation report are contributed by the Stratix® 10 IOPLL and H-tile transceiver PLLs. For Stratix® 10 device 1ST280EY2F55, the total 64 PLLs consist of 24xIOPLLs, 8xfPLLs of H-tile, 8xATX PLLs of H-tile transceiver, and 24 CDR PLLs of H-tile transceiver. Stratix® 10 FPGA E-tile transceiver channel PLLs are not counted. The problem has been fixed starting with Quartus® Prime Pro Edition software version 19.3.Why does the RSU update cause the HPS to hang in Stratix® 10 FPGA devices with bitstreams containing large fabric designs from Quartus® Prime Pro version 25.1.1 and earlier?
Description Due to a problem in the calculation of a timeout value by the System Design Manager (SDM) firmware during the Remote System Update (RSU) process in Stratix® 10 FPGA devices, the Hard Processor System (HPS) hangs because of an SDM timeout expiration. The timeout is determined by multiplying the fabric design size in the bitstream by 10,000 and storing the result in a 32-bit variable. For large fabric designs, this value exceeds the 32-bit limit, causing it to wrap around to a smaller number. This leads to a short timeout value, and therefore a timeout expiration. The problem occurs in the FPGA Configuration First boot mode and affects Quartus® Prime Pro Edition releases 25.1.1 and earlier with bitstreams from those releases. Resolution The problem has been fixed starting with Quartus Prime Pro Edition software version 25.3.Why do I see cache coherency problems between the HPS and FPGA on HPS designs using ACE-Lite interfaces in Intel Quartus Prime Pro version 20.4 and earlier?
Description Due to a problem in the Intel© Quartus© Prime Pro software version 20.4 and earlier, incorrect AXI signal values may be seen on transactions between ARM® AMBA® AXI ACE-Lite Managers using the ARM AXI ACE-Lite protocol to connect to other logic in Platform designer, such as HPS FPGA to SOC Bridges or Avalon® Agents. This may be seen at run time as cache coherency errors. Resolution Patch 0.28 for the Intel® Quartus® Prime Pro software version 20.4 is available to fix this problem. Download and install the patch from the relevant link below, and re-compile your design. quartus-20.4-0.28-linux.run quartus-20.4-0.28-windows.exe quartus-20.4-0.28-readme.txt This problem is fixed in the Intel© Quartus© Prime Pro software version 21.1When does the Quartus® Prime Design Software, IP cores, and Questa*-Altera® FPGA Edition Software check out a license?
Description Below is a description of how the Quartus® Prime Design Software, IP cores, and Questa*-Altera® FPGA Edition Software utilize licenses: Resolution Quartus® Prime Design Software: All Quartus® Prime Design Software processes check for a valid license, including the Quartus® GUI, Analysis & Synthesis, Assembler, and TimeQuest Timing Analyzer. These processes start only if a valid license is available. They do not hold or occupy the license; they only validate that one is available. However, the Fitter checks out a license when it starts and holds it for the duration of the Fitter process. IP cores: A license for an IP core is checked out when the Quartus® Prime Design Software opens the first encrypted file of the IP core for synthesis. This license is held for the duration of synthesis. The Assembler checks out the license for every IP core to create the programming file and holds it for the duration of the Assembler process. Questa*-Intel® FPGA Edition software: Once Questa*-Intel® FPGA Edition Software loads a design unit during elaboration, a Questa-Intel® FPGA Edition license is checked out. It remains checked out until the simulation ends (quit -sim), or the simulator is closed. Once a waveform is loaded into the simulator, a Questa*-Intel® FPGA Edition Software license is also checked out for viewing Wave Log Format File (.wlf), and it remains checked out until the waveform window is closed. Related Articles What happens to a license if the Quartus II software terminates unexpectedly? Can I perform multiple compilations using the Quartus II software at the same time on one computer with a one seat floating license or one fixed (node locked) license file?