Why does Board Support Package (BSP) Editor in Quartus® Prime Pro Embedded Edition fails to generate Nios® V processor BSP project from .vds file?
Description Due to a problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, the BSP Editor fails to generate Nios® V processor BSP project from .vds file. This issue is not affecting BSP project generation: From .qsys file using BSP Editor in Quartus® Prime Pro Embedded Edition software, or Using BSP Editor in Quartus® Prime Pro Edition software. This issue is caused by a software bug in the BSP Editor of Quartus® Prime Pro Embedded Edition software. Refer to Nios V Embedded Processor Design Handbook - Recommended Tools from Quartus Prime Installer (PDF) for more information on the difference between Quartus® Prime Pro Edition and Quartus® Prime Pro Embedded Edition software. Resolution To work around this problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, apply either one of the workarounds below: Switch from .vds to .qsys file Use BSP Editor in Quartus® Prime Pro Edition software version 26.1 or 26.1.1 This problem is currently scheduled to be resolved in a future release of the Quartus® Prime Pro Embedded Edition Software./quartus/pgm/bitasm/bitasm_bitstream_encryption.cpp, Line: 1439 Expected the extra routing value(8) to be 0 or 4.
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3, this error message might be displayed when generating an encrypted FPGA bitstream file using the quartus_pgm tool. This problem only affects some FPGA bitstream files. Resolution This problem is fixed beginning with version 26.1 of the Quartus® Prime Pro Edition Software.Why does "Display in New Tab" fail in the RTL Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you might see that "Display in New Tab" does not work for components in a design partition. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 25.3.1, download and install patch 1.27. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why can't the Altera FPGA IP Evaluation Mode be disabled?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might encounter the problem above where the warning message below does not appear even though the Altera® FPGA IP Evaluation Mode has been disabled. Warning Message: "Warning(23202): Intel FPGA IP Evaluation Mode feature is not used – it has been explicitly disabled for this design" Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 26.1.Why do I see unconstrained "am_muxsel_gen_inst|async_out" clocks within the Stratix® 10 E-Tile CPRI PHY IP core in timing report for example design?
Description When you compile Stratix® 10 E-Tile CPRI PHY IP example design in the Quartus® Prime Pro Edition software version 19.2, you will see below highlighted unconstrained clocks. dut_wrapper|dut|alt_cpriphy_c3_0|SL_SOFT_I[0].sl_soft|latency_measure_inst|am_muxsel_gen_inst|async_out dut_wrapper|dut|alt_cpriphy_c3_0|SL_SOFT_I[1].sl_soft|latency_measure_inst|am_muxsel_gen_inst|async_out dut_wrapper|dut|alt_cpriphy_c3_0|SL_SOFT_I[2].sl_soft|latency_measure_inst|am_muxsel_gen_inst|async_out dut_wrapper|dut|alt_cpriphy_c3_0|SL_SOFT_I[3].sl_soft|latency_measure_inst|am_muxsel_gen_inst|async_out Resolution These are not valid warnings. The nodes highlighted are not clocks. They are safe to be ignored.Fatal Error: hipi_ok, BSYN_QI_LABMGR::sync_lchip_lab + fitter_bsyn
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1, you might encounter this error while compiling a Partial Reconfiguration (PR) Implementation Revision design. Resolution This problem will be fixed in Quartus® Prime Pro Edition Software version 26.1.1 release onwards. No fix is planned in Quartus® Prime Pro Edition Software version 26.1. If you encounter this Quartus IE, file a service ticket through Altera Premier Support (APS) system for a software patch.
Why is there an "unrecognized device" error when using quartus_jli to configure or program a JAM file for flash devices of 2 GB or larger?
Description In any versions of Altera® Quartus® Prime Pro Edition Software, the quartus_jli command may report an “unrecognized device” error when a JAM file targets a flash device that is 2 GB or larger. This behavior is specific to JAM files used with large flash devices and does not occur with smaller flash sizes. Resolution Use the following workaround to avoid the error: Run the jtagconfig command to detect the connected JTAG hardware. After the hardware is detected, run quartus_jli to configure or program the JAM file. There is currently no plan to fix this behavior in a future Quartus® Prime release.Why are my high fanout cells not duplicated?
Description Due to an problem in the Quartus® Prime Pro Edition Software versions 24.3 and later, duplication of cells with high fanout is prevented even when duplication assignments such as DUPLICATE_REGISTER or DUPLICATE_SYNC_FANIN are defined explicitly. This behavior affects cells that have a driver in a different partition, including both signals and clocks. For example, a register in partition A that has its clock coming from the root partition will not be duplicated despite having the appropriate assignment. Resolution To work around this problem, remove the partitions or ensure that the affected cells are not driven by other cells in different partitions. If removing partitions from your design is not feasible, patches are available to work around this problem. Download and unzip the zip file that matches your Quartus® Prime Pro version and operating system from this KDB. Quartus® Prime Pro Edition Version Patch number 24.3 [0.36|^quartus-24.3-0.36.zip] 24.3.1 [1.30|^quartus-24.3.1-1.30.zip] 25.1 [0.38|^quartus-25.1-0.38.zip] 25.1.1 [1.29|^quartus-25.1.1-1.29.zip] 25.3 [0.28|^quartus-25.3-0.28.zip] 25.3.1 [1.07|^quartus-25.3.1-1.07.zip] Patches for versions 25.3 and 25.3.1 also address additional problems; refer to the README files for more information. This problem is fixed beginning with the Quartus® Prime pro Edition Software version 26.1.Error(23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: pio_1_2
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you might see the error above when using the I/O PLL Parameterizable Macro (ipm_iopll). The error only occurs when using non-integer values for the VCO Clocks and Output Clocks in the I/O PLL Parameterizable Macro. Resolution To work around this problem, use non‑integer values for the VCO Clocks and Output Clocks in the IOPLL IP. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.drivers/src/altera_s10_mailbox_client.c:32:59: error: 'OS_FLAG_SET' undeclared (first use in this function); did you mean 'ALT_FLAG_SET'?
Description Due to a problem in Quartus® Prime Pro Edition Software, you might see an error when compiling Nios® V software with the Mailbox Client IP or 16550 Compatible UART Core driver, in FreeRTOS environment. This is because the driver software of the IP is using “MicroC/OS-II”-specific OS_* macros. Resolution The recommended macros are the OS-independent ALT_* macros. MicroC/OS-II Real-Time Operating System - Thread-Safe HAL Drivers FreeRTOS Real-Time Operating System - Thread-Safe HAL Drivers Replace the OS_* accordingly. MicroC/OS-II Macros Replace to OS_FLAG_SET ALT_FLAG_SET OS_FLAG_CLEAR ALT_FLAG_CLEAR OS_FLAG_WAIT_SET_ALL ALT_FLAG_WAIT_SET_ALL_WO_CONSUME (OS_FLAG_WAIT_SET_ALL + OS_FLAG_CONSUME) ALT_FLAG_WAIT_SET_ALL_WITH_CONSUME OS_FLAG_WAIT_SET_ANY ALT_FLAG_WAIT_SET_ANY_WO_CONSUME (OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME) ALT_FLAG_WAIT_SET_ANY_WITH_CONSUME OS_FLAG_GRP* group ALT_FLAG_GRP(group)
