Why does the Nios® V/g processor become unstable when both CLIC and shadow registers are enabled?
Description Due to a problem in the Quartus® Pro/Standard Edition software version 26.1/25.1, Nios® V/g interrupt handling might be unstable when both CLIC mode and Shadow Register are enabled. This is because the Shadow Register CSR (msrfstatus) is not saved/restored during interrupt context saving under CLIC mode. Resolution To work around this problem in the Quartus® Prime Pro/Standard Edition Software version 26.1/25.1, follow these steps: Download the machine_trap.zip Extract to get the new machine_trap.S Search for the old machine_trap.S in your BSP project Replace with the new machine_trap.S file Rebuild your software Additional Information This problem is currently scheduled to be resolved in a future release of the Quartus® Prime Pro and Standard Edition Software.Error: CPU "intel_niosv_g_0" has no memories connected to its Avalon host(s)
Description Due to a problem in the Quartus® Pro Edition software version 26.1.1, you might see an error when generating a Nios® V BSP, when the AXI Address Span Extender IP is inserted between the Nios V processor and the memory device connected to the instruction and data buses of the Nios V. This is because the AXI Address Span Extender IP does not recognize the connected device as a memory device for the Nios V processor. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 26.1.1, follow these steps: 1. Open <QUARTUS_INSTALL_DIR>/ip/altera/merlin/axi_address_span_extender/axi_address_span_extender_hw.tcl 2. Go to around line 448, then delete the lines marked in red and add the lines marked in green as shown below. # this assignment allows this component to appear as a memory target in the Nios II linker script configuration GUI # it makes the memory map of our slave look like a valid linker target memory region # <<to be revisited in 13.0>> - #set_interface_assignment windowed_slave embeddedsw.configuration.isMemoryDevice 1 + set_interface_assignment $slave embeddedsw.configuration.isMemoryDevice 1 # # this assignment allows the macros of components attached to our master to appear in the Nios II system.h header # <<to be revisited in 13.0>> - #set_interface_assignment windowed_slave embeddedsw.configuration.affectsTransactionsOnMasters "expanded_master" + set_interface_assignment $slave embeddedsw.configuration.affectsTransactionsOnMasters $master Please do not include the leading "+" and "-" characters. 3. Regenerate your design in Platform Designer. Additional Information This problem is currently scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software. However, the updated statements are commented out by default. To apply the changes, remove the comment markers.Why don’t the new Nios® V/c processor features appear after upgrading the Nios® V/c Processor IP to Quartus® Prime Pro version 26.3?
Description In Quartus® Prime Pro Edition 26.3, the Nios® V/c processor IP is renamed from intel_niosv_c to niosv_c across all FPGA device families. Performing IP Upgrade from earlier Quartus® Prime project will retain the legacy intel_niosv_c in your project. For your information, This legacy intel_niosv_c IP remains at last updated back in Quartus® Prime Pro Edition 26.1.1. While new Nios® V/c processor IP feature are introduced into niosv_c IP starting from Quartus® Prime Pro Edition 26.3. In another words, auto-upgrade of intel_niosv_c to niosv_c in not supported by IP Upgrade. Thus, you may find those new Nios® V/c processor features (in niosv_c) is missing in intel_niosv_c. Resolution If new Nios® V/c processor features (such as Debug option) is required, re-instantiate the Nios® V/c processor in Quartus® Prime Pro version 26.3.Why is the HPS I2C SCL clock frequency above 400 kHz in fast mode when using U-Boot?
Description When the HPS I2C controller is configured for fast mode (clock-frequency = <400000>) in U-Boot, the measured SCL frequency might exceed the 400 kHz maximum in the I2C specification (for example, 431 kHz) on SoC FPGA designs. This happens because the U-Boot DesignWare I2C driver (drivers/i2c/designware_i2c.c) calculates the SCL high and low counts from assumed SCL rise and fall times. When the device tree does not specify them, the driver assumes default 300 ns for both in fast mode. The driver subtracts the assumed rise time from the SCL period. If the board's actual SCL rise time is shorter than 300 ns, the unused part of that allowance shortens the period, and SCL runs faster than 400 kHz. The Linux DesignWare I2C driver uses a different calculation and different device tree properties, so the same device tree node can give different SCL frequencies in U-Boot and Linux. Resolution To set the SCL timing to match your board, follow these steps: Measure the SCL and SDA rise times (30%–70%) and fall times (70%–30%) on your board with an oscilloscope, in fast mode. In the U-Boot device tree, add the measured values to the HPS I2C node: &i2c0 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <[measured tr]>; i2c-scl-falling-time-ns = <[measured tf]>; i2c-sda-hold-time-ns = <[required hold, default 300]>; }; For Linux, add the SDA fall time to the same node. The Linux driver uses i2c-sda-falling-time-ns for the SCL high count and i2c-scl-falling-time-ns for the SCL low count, and ignores i2c-scl-rising-time-ns: i2c-sda-falling-time-ns = <[measured tf]>; Rebuild U-Boot and the Linux device tree blob, then re-measure SCL in both U-Boot and Linux to confirm the frequency is at or below 400 kHz and that tLOW ≥ 1.3 µs and tHIGH ≥ 0.6 µs. Note these points when tuning: In U-Boot, enter the actual measured rise time. A larger i2c-scl-rising-time-ns value makes SCL faster, not slower. In U-Boot, i2c-scl-falling-time-ns changes only the high/low duty cycle, not the frequency. In Linux, larger fall-time values make SCL slower. Do not lower clock-frequency below 400000 in U-Boot to slow the bus. Any value below 400000 selects standard mode (100 kHz timing). snps,bus-capacitance-pf has no effect in fast mode. U-Boot ignores it, and Linux uses it only for high-speed mode (3.4 MHz). Additional Information Property U-Boot Linux clock-frequency Sets the target SCL period (default 100 kHz) Selects the speed mode only (default 400 kHz) i2c-scl-rising-time-ns Sets the SCL frequency (default 300 ns in fast mode, 1000 ns in standard mode) Ignored by the DesignWare driver i2c-scl-falling-time-ns Changes the duty cycle only (default 300 ns) Sets the SCL low count (default 300 ns) i2c-sda-falling-time-ns Ignored Sets the SCL high count (default 300 ns) i2c-sda-hold-time-ns Sets the SDA hold time (default 300 ns) Sets the SDA hold time (default: keeps the existing hardware value) snps,bus-capacitance-pf Ignored Used in high-speed mode (3.4 MHz) onlyWhat are the issues in Nios® V processor for designs targeting Agilex® 27 FPGA device?
Description Due to a problem in the Quartus ® Prime Pro Edition software version 26.3, Nios® V Debug IP fails to execute dmcontrol.hartreset on a halted Nios® V processor. This is because there is a bug in Nios® V/c processor, when servicing dmcontrol.hartreset request while halted. If the processor is a running state, dmcontrol.hartreset can be executed successfully. Resolution To work around this problem in the Quartus ® Prime Pro Edition software version 26.3 (select one), Use dmcontrol.ndmreset to reset the processor at any states. Use dmcontrol.hartreset only when the processor is at running state. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.Why do I get the error "Verilog HDL error at name_of_file.sv (XXX): Name_of_parameter is not declared under the prefix 'Name_of_interface'" when using nested interface instances with parameters in Quartus® Prime Pro 26.1 and earlier?
Description When using nested interface instances with parameters in Quartus® Prime Pro 26.1 and earlier, compilation may fail with the following error message: Verilog HDL error at name_of_file.sv (XXX): Name_of_parameter is not declared under the prefix "Name_of_interface" This issue can occur when a parameter is referenced through a nested interface hierarchy and is not correctly resolved during compilation. Resolution This issue has been fixed in Quartus® Prime Pro 26.1.1. If a patch for an earlier version is required, please contact Altera Support and reference patch ID QS-20872.Why does compilation fail after restoring a project archive?
Description Due to a problem in the Quartus® Prime Pro Edition software Windows version 26.1.1, an archived project that compiles successfully before may fail to compile after it is restored from a Quartus Archive File (.qar). Some IP-generated files may be missing from the restored project. Resolution To work around this problem, open your project from the QAR file and change the following IP Generation settings: Open Assignments → Settings → IP Generation. Select VHDL as the IP generation language. Note: Do not regenerate the IP.Why I can't change the device family in Power and Thermal Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1, you may not be able to change to a different device family in Power and Thermal Analyzer (PTA) after you create or open a design. For example, if you open a design targeting a Stratix® 10 device, you may not be able to change to an Agilex® FPGA device. In version 26.1, if you select File > New File to create a new PTA design, the new file wizard does not appear. Without the wizard, you cannot select a different device family when creating a new file. Resolution PTA locks a design to the device family selected when the file is created. To explore power consumption across different device families, create a new PTA file in the target family and import your existing design. To import an existing PTA design into a different device family: Create a new PTA file targeting the desired device family. Use the Import function to bring your existing PTA design into the new file. If you chose the wrong device family when creating a file, close the existing file and create a new one. In the File menu, select New File, and select the correct device family in the new file wizard. In version 26.1 of Power and Thermal Analyzer, the new file wizard does not appear when you select New File. To work around this issue, exit and restart PTA. After restarting, select File > New File to open the new file wizard and select the correct device family.Why does Quartus® Prime Pro give an error when trying to route HPS reset signals, such as s2f_rst or s2f_cold_rst, to the Fabric using the localized Sector Clock Network?
Description Due to device architecture requirements in Altera® SoC FPGA families with a Hard Processor System (HPS), the Quartus® Prime Pro Edition Software version 25.3.1 reports a fitter routing error when you try to route certain HPS-to-FPGA reset signals to the FPGA fabric using the localized Sector Clock Network instead of the Global Clock Network. In the Agilex® FPGA architecture, there is a device-wide Global Clock Network (meant for high fan-out signals) and a localized Sector Clock Network (meant for low fan-out, smaller regional scope, or localized logic structures). Certain signals, such as s2f_rst or s2f_cold_rst, are restricted to be only on the Global Clock Network. For example, if you use: set_instance_assignment -name GLOBAL_SIGNAL OFF -to ...|hps_inst|s2f_cold_rst Quartus reports an error similar to: Error (170084): Can't route signal "...|hps_inst|s2f_cold_rst" to atom ... Resolution Certain signals, such as s2f_rst or s2f_cold_rst, are restricted to be only on the Global Clock Network. To work around this routing error in the Quartus® Prime Pro Edition Software: Remove any instance assignment that sets GLOBAL_SIGNAL to OFF for HPS-to-FPGA reset outputs (for example, s2f_rst or s2f_cold_rst). Recompile the design and allow Quartus to route these reset signals on the Global Clock Network. This behavior reflects device architecture and fitter rules; it is not scheduled to be changed to allow HPS-to-FPGA reset signals on the Sector Clock Network.Why does the SystemConsole.refreshMasters DSP Builder function fail?
Description When using the SystemConsole.refreshMasters DSP Builder function in the Quartus® Prime Pro Edition version 26.1.1 and above, you may see the following error: Unable to resolve the name 'com.altera.systemconsole.matlabapi.SystemConsoleLink' This error occurs because the Java version used by MATLAB is incompatible with com.altera.systemconsole.matlabapi.SystemConsoleLink. For DSP Builder version 26.1.1 and later, MATLAB must use Java version 11 or later for SystemConsole.refreshMasters to run successfully. Resolution You can change MATLAB's Java version using either the jenv MATLAB function or the matlab_jenv executable. For information on how to use jenv and matlab_jenv, refer to the MATLAB documentation.