Why is the configuration space wrong for upstream port or downstream port of P-Tile Switch IP after a host reboot while FPGA remains powered on?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 23.3 and earlier, you might see this error if PCIe* Compliance Support option disabled.

A combination of unsynchronized reset (PERST) and Safe Sequential state machine encoding causes incorrect state transition of the read/write address encoder FSM of the configuration RAM during the initialization sequence of the PCIe switch. This results in incorrect writes to the DS or US port registers.

Resolution

User should synchronize the PERST signal of the PCIe Switch IP top-level to the app_clk domain. Alternatively, user can generate the PCIe Switch IP with PCIe Compliance Support enabled in Quartus 23.3 and earlier.

This problem has been fixed in the Quartus® Prime Pro Edition Software version 23.4 or later.