power
114 Topicsreduced VCCL_SDM, VCCPLLDIG_SDM on A5E
The SmartVID parts list VCCcore and VCCP able to be varied from 0.7 to 0.9V. however- VCCL_SDM, VCCPLLDIG_SDM have a specified minimum of 0.78. They require the VCCL_SDM, VCCPLLDIG_SDM at 0.8V. IE needs extra power plane and power supply regulator. I need to understand when using -2V or -3V devices : What are the functional impacts of tying VCCL_SDM, VCCPLLDIG_SDM to VCCcore ? What limitations am I likely to encounter at VCCL_SDM, VCCPLLDIG_SDM being at 0.725, 0.7V ? (SDM and PLL clock speeds I am guessing ) It is accepted that VCC_HSSI must remain at datasheet spec. (2) How can I vary VCCcore in the power thermal analyser (PTA) ? the TCL commands dont seem to be able to vary these voltages to look at effect of static power consumption. Is there a model in the current PTA to be able to characterise this ? Reason for this is to lower static power as much as possible (when the device is not busy - IE clock speeds can be lowered). In Xilinx, the DSP block cascade Fmax breaks first, and some PLL max F. with thanks glen.Solved72Views0likes5CommentsIntroducing the Altera Community AI Responder — Beta
Altera is introducing the AI Responder, an assistant built into the Altera Community to help provide faster, context-aware guidance for Altera product questions. It uses relevant public Altera documentation and Knowledge Database content, with coverage continuing to expand. The AI Responder may provide source references and can hand off complex or out-of-scope questions to an Altera subject-matter expert. As a beta feature, responses may contain errors or omissions, so please review the sources and verify technical guidance against official Altera documentation before implementation. If the response does not fully address your question, add more context and tag ai_responder to continue the discussion. We welcome your feedback as we improve the Community experience.33Views0likes0Commentswhich A3C devices have on chip decoupling capacitors
The PCB capacitor requirements at https://docs.altera.com/r/docs/853726/current/pcb-design-guidelines-agilex-3-fpgas-and-socs/decoupling-capacitors-recommendation Suggest that all A3C devices have small VCCcore, VCCIO decoupling capacitors on package, only needing bulk (>=1uF) external) . However back Feb 26, I read some other Altera document that said there was some migration issue between A3C065 and A3C100 B18A package that A3C025,050,065 had on package decoup, but A3C100/135 did not Please clarify. and any comments on A5E packages welcome. with thanks glen Experienced Xilinx user, defecting.Solved173Views0likes3CommentsUpdated .brd file for Stratix 10 GX dev kit
Referencing this post: EK-10M08E144 PCB .brd file corrupted | Altera Community - 302242 The .brd file that comes in the documentation at: https://www.altera.com/products/devkit/po-3028/stratix-10-gx-signal-integrity-development-kit-h-tile ...was done in Allegro, prior to version 16.6. The only available Allegro viewer gives an error because it was done prior to version 16.6, and you need the DB Doctor utility to update the file. The only way to get the DB Doctor utility is to install Allegro. If I had Allegro...I would not be installing the Allegro viewer. Altera: As mentioned in the post above (well over a year ago), it would make sense for you to update your files so customers can view the board of their $10K+ development board. How do we make that happen? Thanks!529Views0likes4CommentsQuartus Programmer 21.1: JTAG Server Error Code 82 – Port 1309 Cannot Be Bound
Hello Altera Community, I am working on an FPGA project using a Cyclone IV FPGA development board and an Altera USB-Blaster. I am currently unable to program the FPGA because Quartus Programmer cannot access the JTAG server. System details: - OS: Windows 11 64-bit - Software: Quartus Programmer 21.1 - Installation path: C:\intelFPGA\21.1\qprogrammer - Programmer: Altera USB-Blaster - FPGA: Cyclone IV development board The USB-Blaster is detected by Windows Device Manager and the driver is installed. The USB-Blaster also powers on normally. However, Quartus Programmer gives: "Attempted to access JTAG server -- internal error code 82 occurred" When I run: jtagconfig I get: Error when scanning hardware - Server error Sometimes it also hangs at: Connecting to server(s) [...] I checked the JTAG server using: jtagserver --status It reports: Installed JTAG server is 'C:\intelFPGA\21.1\qprogrammer\bin64\jtagserver.exe' Server is stopped Remote clients are disabled I tried reinstalling the JTAG server: jtagserver --install jtagserver --start But the server immediately stops. I also tried: net start "Altera JTAG Server" The result was: The Altera JTAG Server service could not be started. The service did not report an error. NET HELPMSG 3534. I then ran: jtagserver.exe --foreground and received: Unable to bind changedetect socket: 10048 Can't bind to TCP port 1309 - exiting I checked the port using: netstat -ano | findstr 1309 and found that TCP port 1309 was being used/listened to by another process, for example PID 12888. I tried terminating the process using: taskkill /F /PID 12888 but Windows reported: ERROR: The process with PID 12888 could not be terminated. Reason: There is no running instance of the task. I also tried stopping the JTAG server, reinstalling it, and restarting it. In addition, I already tried the following: 1. Disabled PCI Express → Link State Power Management. 2. Disabled USB Root Hub power saving ("Allow the computer to turn off this device to save power"). 3. Stopped the Print Spooler service. 4. Closed Quartus/Programmer-related applications. 5. Reinstalled the JTAG Server. 6. Restarted the computer. 7. Tried starting the JTAG server manually. 8. Checked TCP port 1309 using netstat. The problem still remains. My main questions are: 1. Why is Quartus Programmer 21.1 unable to start the JTAG Server? 2. What is causing TCP port 1309 to remain occupied? 3. Is there a known issue with Quartus Programmer 21.1 and Windows 11? 4. Is there a recommended patch, driver, or newer Quartus Programmer version for this problem? 5. Is it possible to configure the JTAG server to use another TCP port? 6. What is the correct way to completely remove and reinstall the JTAG Server on Windows 11? 7. Is there anything else I should check before reinstalling Quartus Programmer? I would appreciate any guidance on how to get the JTAG Server running so that jtagconfig can detect my USB-Blaster and FPGA. Thank you.269Views0likes5CommentsImpedance measurement on power lines
We are using precision Multimeters in resistance mode and set them at manual 10K range for checking impedances on all power lines (versus ground) of our products. We established Ohm ranges for each power line of a product in order to know if the circuit looks ok before applying power. We have some products that have very sensible parts such as DDR3 memories with 0.75V±0.0375V powers and Altera FPGA with 0.9V±0.03V. By using another multimeter, we measure around 9V between the unconnected probes of different manufacturers precision multimeters set in such 10K range resistance mode. Even if the current is extremely small, we are worried that our sensible parts could be affected by this 9V “glitch”. What does Altera recommend for such measurement ? We are currently using alternative method like putting a Shunt resistor of 1K between the probes in order to keep the voltage near 0V. Of course all our range are now within 0 to 1K Ohm range and when our probes are unconnected, we always get 1.000K displayed. We can manage working with these low ranges. thanksSolved107Views0likes3CommentsMSEL and nCONFIG behavior at power up
Hallo We used the Agilex5 device with Smart VID and AS configuration. The device configured OK, but lately I notice the MSEL pins and nCONFIG pull down during VCCIO_SDM (1.8V), see attached figures, Is it normal behavior? I don't see it on all boards Thanks AsafSolved60Views0likes2Comments