The Verilog code was not actually programmed into the FPGA.
I have a question. I am using a 10M02SCM153C8G FPGA. I wrote a simple program, successfully programmed it onto the development board, and confirmed it produced the intended simple functionality. However, I've noticed that whenever I power cycle the evaluation board (by unplugging and replugging the USB cable), the board reverts to running the original sample code that was pre-loaded. This leads me to believe that although I performed the programming operation, the code was not actually programmed into the FPGA's non-volatile memory. Is there a specific option in the programming interface that I must select to ensure the code is permanently written to the FPGA's internal Configuration Flash Memory (CFM) block? As I recall, the MAX 10 series does not require an external SPI EEPROM for configuration, which I believe is correct. Does this also mean that if I do not select the correct programming option, the code is only loaded into the FPGA's volatile SRAM, and is therefore lost upon power-off?
MAX 10 Instant-On
Hello, I understand the instant-on timing specs to be relaxed per this adjacent post - https://community.intel.com/t5/Programmable-Devices/MAX10-Instant-On/m-p/202216 However, for the sake of deeper understanding, can you please point Me to document #683794 version 2017.12.15 or advise further? I'd like to better understand what was once considered. Thank you,
Cyclone 10 GX continiously increasing power consumption
Hello, We developed two custom evaluation boards (different layouts) using the Cyclone 10CX150YU484E5G FPGA . Our problem is that we face the same increasing power consumption issue in both development boards. Before and after the FPGA placement we measured all the point of loads on the PCB and there was no short circuit. The FPGA is biased correctly in every pin. We also followed the guidelines for the power-up sequence. After placing the FPGA we stated the following issues: 1.The un-programmed FPGA increased gradually the current consumption of the boards and it was also heated a lot. 2. Before the FPGA programming the GPIOs of all the banks outcome "high" values. 3.After the successful FPGA programming through JTAG and AS the rate of the current consumption dramatically increased. Do you have any ideas regarding the cause of this behavioral in any of the above mentioned issues ? Regards,
Extra Power adaptor for Agilex™ 7 FPGA M-Series HBM2e Development Kit
Hi, To start using the Ethernet (except loop-back), the documentation writes: "All the QSFPDD and QSFPDD800 ports can support up to class 8, meaning each port consumes 18 W. Two power supplies are needed to provide sufficient power for peak performance." (section 3.2). I have looked to buy an identical one that is supplied with the kit, but they seem hard to find, and alternative power adapters that are 12V/250W (like the one supplied with the kit) with a PCIe (Molex Mini-Fit Jr.) connector is hard to find. Could you kindly advise on where to find such power adapters? Thanks in advance.The issue encountered when programming the POF file into MAX10
After powering on my FPGA development board, the power status LED did not light up, so I checked it and found that the issue was with the MAX10 chip. I then planned to reprogram the MAX10 using the max10_bmc.pof file located in the factory_recovery/max10_recovery directory in BTS. However, during the programming process, Quartus reported the following error: Error(209015): Can't configure device. Expected JTAG ID code 0x031050DD for device 1, but found JTAG ID code 0x020D10DD. Make sure the location of the target device on the circuit board matches the device's location in the device chain in the Chain Description File (.cdf).
