Quartus and power domain
We actually one remaining pending issue with the Agilex chip that we can't get resolved and might need some help. The basic description is that when comparing the power consumption of the Agilex 5 on our module, to the Agilex 5 on the dev kit, at same temperature, before any configuration, our Agilex 5 consumes about 0.5-1W more. Besides this, all sub-systems seem to operate correctly (CPU, memory, FPGA, I/Os). This additional power consumption is worrying though, and we would like to understand it before spinning the next revision. Regarding the excess power on our board, it might also be a design issue, but we didn't find any hint yet despite multiple deep reviews and investigations. We already spent several weeks looking at this in every way we could think about, so there is already quite a bit of things we tried out, such as: - Measured the power rails, from the outside and from the inside as well, checking if there is any unexpected difference - Measured temperature from the outside (thermal camera) as well as from the multiple internal sensors - Reviewed power sequence, playing with various combinations to see if it made any difference - Reviewed multiple times schematics against documentation and dev kits The extra power is on the core rail. Now please look at the attachement: We collected side observations on an non-configured FPGA. Our board has a temperature-dependent power consumption. So we simply switched the fan off for a short period and then switched it back on. The main power consumption is on the 0.8 V rail (U500 RAA210130). A second interesting observation is the internal temperature of the Agilex: L0_0 is significantly hotter than the other three. When the fan is switched back on, the power consumption returns to its initial value. Very strange and unusual behavior. Could this somehow help set priorities and allow us to rank the most/least likely directions for investigating the source of the elevated power consumption?Power-Down Sequence Requirements for the Agilex 7 F-Series(2x F-Tile) Devices
Hi, Is there any power down sequence for Agilex 7 F-Series (2x F-Tile) Devices? I went through Agilex™ 7 Power Management User Guide, which lists power down sequence for Agilex 7 Devices with E-Tile & Agilex 7 M-Series Devices bit i could not find for F-Series (2x F-Tile) Devices. Thanks in-advance, Deva
Why does PTA show zero W for F-tiles in Hierarchical Design Editor
Why is there no power shown in the Hierarchical Design Editor(25.3: Current Level Dynamic Power, 26.1: Self Dynamic Power) when adding a fully utilized F-tile? The Total Power does however show the expected power. Is it a bug or a feature?
Regarding Power-Up Sequence for Agilex 5
Regarding the power sequencing of Agilex 5, the required power-up sequence is specified in the documentation. However, in our case, the sequence was not properly followed. Could you please advise what kind of impact may occur on the FPGA if voltages are applied under such a condition where the specified power sequence is not met? Power Management User Guide: Agilex 5 FPGAs and SoCs https://docs.altera.com/viewer/book-attachment/PgABpvRJy7P6fU_ZAXzUJw/zAjQMZanXPEHuIot~~5CbA-PgABpvRJy7P6fU_ZAXzUJw
Agilex 7 Decoupling capacitor scaling factor
Hi! I have got my power estimate from quartus prime based on our requirement, which is " board's power consumption". Now to find the scaling factor i need to know the "maximum power per power rail" , where would i get this value? is it related to FPGA part(AGFB027R24C2I2V) or the max current rating of my convertors? Thanks, Vigneswaran
Power consumption between Agilex3 and Microchip Polarfire FPGA
Microchip claim their FPGA has lower power consumption than SRAM based FPGA , no matter how advanced node used for Altera. is there an official feeback to those claim ? if customer design is battary powered and really care power consumption rather than fabric or tranciever performance, what is the advantage of Agilex 3 comparting to Microchip Smartfusion and Polarfire in power consumption. has Altera done any comparision regarding power consumption ? Any comparision data availalble to share? https://www.microchip.com/en-us/products/fpgas-and-plds/low-power Microchip FPGAs and SoC FPGAs consume up to 50% lower total power than competitive FPGAs. Our nonvolatile process delivers FPGA families that are live at power-up with minimal in-rush current, and significantly lower leakage than SRAM-based alternatives
Error : Arria 10 emif_reset_ interrupt acknowledge
Hi All, I am currently working with an Arria 10 FPGA on a custom board and have encountered an issue where the PCB restarts after the following error message appears: "Error: Arria 10 EMIF reset interrupt acknowledge" I have verified all supply voltages and clock signals, and they are within the expected ranges. Initially suspecting a DDR-related issue, I replaced the DDR component; however, the problem persists. Additionally, all status pins appear to be functioning as expected. I would appreciate any guidance or suggestions on how to further debug this issue. Thank you in advance for your support.
Cyclone 5 SoC FPGA Bank Supply Prerequisite
Dear Altera Support Team, I am not sure this is correct and did not found much info on Handbook. Device 5CSXF6C6U23 CASE 1: BANK 5A 5B only supplied VCCPD to 2.5V and VCCIO is floated. JTAG scan chain shows both HPS and FPGA devices. JTAG program shows failed with wrong device address. CASE 2: BANK 5A 5B supplied 2.5V or 1.8V VCCIO. JTAG scan chain shows both HPS and FPGA devices. JTAG program shows successful result. Based on the above situation: do BANK 5 must supplied VCCIO in order FPGA to work? I don't understand, other brand FPGA do not have such requirement while VCCPD must be powered which is understandable. Please confirm this for best and safe device HW configuration. Thanks, Brian
