Can I program Altera in-system programmable (ISP) devices concurrently?
Description Yes, you can program Altera® devices that support ISP concurrently within a particular device family. When the Joint Test Action Group (JTAG) ISP Clock (TCK) is run at high frequencies (1 to 10 MHz), the time necessary to shift data and address information into the device becomes negligible compared to the programming pulse time for the memory cells. When programming multiple devices in a JTAG chain, concurrent programming allows the programming pulses for each of the devices to be applied simultaneously. Thus, this concurrent programming allows programming times to be significantly reduced. When the TCK is run at low frequencies (~100 kHz), the time necessary to shift data and address information into the device becomes dominant as compared to the programming pulse time for the memory cells. Thus at these lower frequencies, concurrent programming has negligible benefits. Altera supports concurrent programming when using Serial Vector Format files (.svf), Jam™ files (.jam), and Jam Byte-Code files (.jbc). These file formats automatically use concurrent programming whenever more than one device, of the same family, is targeted. For more information, refer to In-System Programmability Guidelines for MAX II Devices (PDF) and AN 100: In-System Programmability Guidelines (PDF).SEVERE: java.io.IOException: Get master service paths failed!
Description This error may be seen in the bts_log.txt file in the examples/board_test_system folder of the Intel® Stratix® 10 TX Signal Integrity Development Kit Installer Package when the connection of the Board Test System (BTS) / Clock Controller / Power Monitor GUI fails but you can still auto-detect both the system MAX V and Intel® Stratix® 10 TX in the Intel® Quartus® Prime Programmer. Resolution You can confirm if this error is caused by abnormal behavior of the system MAX V (U8) by using the command get_service_paths master in System Console and checking that this does not return the master information. To fix this error, reprogram U8 with max5.pof which can be found in the examples/max5 folder of the Intel® Stratix® 10 TX Signal Integrity Development Kit Installer Package.Error: TBBmalloc: skip allocation functions replacement in ucrtbase.dll: unknown prologue for function _msize
Description Due to a problem in the Quartus® Prime Standard Edition Software version 24.1 or earlier, you may see this error message when generating Altera® IP on the Windows* 11 OS (Operating System). Resolution To work around this problem, follow these steps: Go to This PC, right-click, and select Properties. Click Advanced System Setting. In the Advanced tab, select Environment Variable. Under System variables, create a new variable with the name TBB_MALLOC_DISABLE_REPLACEMENT and value as 1. Click OK and restart the Quartus® Prime Software.Why does the Pin Planner display incorrect differential pin pairs for device migration in MAX® V devices?
Description Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 21.1 and earler, the Pin Planner displays incorrect differential pin pairs that can't be use for device migration in MAX® V devices. When a migration device is added in the Migration Devices feature, the Pin Planner display only pins that can be used for device migration. When Show Differential Pin Pair Connections is enabled, it displays red lines that show differential pin pairs. But those red lines might not display differential pin pairs that can be used for device migration. For example, when 5M570ZF256 is selected as a current device, 5M1270ZF256 is selected as a migration device, and Show Differential Pin Pair Connections is enabled, the Pin Planner shows the following diagram. Although there are many red lines for differential pin pairs, only the differential pin pairs enclosed by green can be used for device migration. Figure 1. Pin location diagram in the Pin Planner Resolution To work around this problem, manually check if both pins of each differential pin pair have the same pin locations and the same polarity between a current device and a migration device by comparing the pin-out files. In pin-out files of MAX® V devices, find the Emulated LVDS Output Channel column that displays the name of the differential pin. DIFFIO_<symbol>p and DIFFIO_<symbol>n are a differential pin pair. For example, DIFFIO_L1p and DIFFIO_L1n are a differential pin pair. The following are examples of how to check if a differential pin pair can be used for device migration: In 5M570ZF256, Pin C2 is DIFFIO_L1n and Pin C3 is DIFFIO_L1p. But in 5M1270ZF256, Pin C2 is DIFFIO_L1n and Pin C3 is DIFFIO_L2p. They are not a differential pin pair in 5M1270ZF256. The pin pair of C2-C3 can't be used for device migration. In 5M570ZF256, Pin R9 is DIFFIO_L11n and Pin T9 is DIFFIO_L11p. In 5M1270ZF256, Pin R9 is DIFFIO_L13n and Pin T9 is DIFFIO_L13p. The pin pair of R9-T9 is a differential pin pair and has the same polarity in both 5M570ZF256 and 5M1270ZF256. The differential pin pair of R9-T9 can be used for pin migration. This problem has been fixed since Intel® Quartus® Prime Standard Edition Software version 22.1.Why does Questa* license fail to install in the Quartus® Prime Lite Edition Software version 24.1?
Description This problem is due to user setup changed to new NIC ID. The license does not match the current NIC ID. Resolution To workaround this problem, you need to regenerate the license using new NIC ID then update the environment variable method and restart the computer to get the license to operate properly.Why is the input register not registered in the negative input pins, rx_in[*](n) of the ALTLVDS_RX megafunction?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 23.1 and earlier, you might see that the input register is not registered in the ALTLVDS_RX megafunction's negative input pins, rx_in[*](n). This is because the synthesis attributes "LVDS_RX_REGISTER=LOW" and "LVDS_RX_REGISTER=HIGH" are not assigned to the register in the Low-voltage differential signaling (LVDS) receiver interfaces. Resolution To work around the problem, add the following assignments in the Quartus® Settings File (.qsf): set_instance_assignment -name LVDS_RX_REGISTER LOW -to "altlvds_rx:ALTLVDS_RX_component|altlvdsrx_lvds_rx:auto_generated|altlvdsrx_lvds_ddio_in:ddio_in|ddio_l_reg" set_instance_assignment -name LVDS_RX_REGISTER HIGH -to "altlvds_rx:ALTLVDS_RX_component|altlvdsrx_lvds_rx:auto_generated|altlvdsrx_lvds_ddio_in:ddio_in|ddio_h_reg" This problem is currently scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Error (21075): The junction temperature range value of '[-40 C, 100 C]' is illegal for the currently selected part.
Description In the Quartus® II software version 13.1, you may see this fitter error if you compile a design targetting a Max® V device in the industrial temperature range that was created in an earlier version of the Quartus II software. The Quartus II software version 13.0 SP1 and earlier, supported the industrial temperature range for Max V devices. Beginning with the Quartus II software version 13.1, MAX V devices only support the extended temperature range. Resolution To avoid this error, change the following setting in the Quartus Setting File (.qsf) before compiling in later version of the Quartus II software. From: set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 To: set_global_assignment -name MAX_CORE_JUNCTION_TEMP 125If an Altera® FPGA features MultiVolt I/O interface capability, can VCCIO be varied dynamically without reconfiguring the Altera® FPGA?
Description Altera® FPGAs that feature MultiVolt I/O interface capability, VCCIO must not be varied dynamically or without reconfiguring the device. Resolution However, the power supply voltage of the Altera® FPGA driving the MultiVolt input may be varied dynamically within limits specified in the Altera® FPGA documentation for the chosen value of VCCIO.Does Altera provide rise and fall time specifications for the JTAG input signals TCK, TMS, and TDI?
Description Altera® does not provide rise and fall time specifications for the JTAG input signals TCK, TMS, and TDI. You can refer to the Input Signal Edge Rate Guidance (PDF) White Paper for further guidance on this topic. Related Articles What is the rise and fall time requirement for the JTAG data (TDO) going to the USB Blaster? What are the recommended rise and fall time specifications for Altera® devices?Error: No spd files are included in quartus project
Description In the Intel® Quartus® Prime Standard Edition Software version 17.1, the error message above may be seen while executing the ip-setup-simulation script on a project targeting a device that doesn't belong to the Intel® Arria® 10, Intel® Stratix® 10, or Intel® Cyclone® 10 families. The ip-setup-simulation script requires an Intel® Arria® 10, Intel® Stratix® 10, or Intel® Cyclone® 10 Platform Designer folder structure to work properly. Resolution To work around this problem, switch from using the ip-setup-simulation script to the ip-make-simscript script. For more information on the ip-make-simscript script usage, please consult the Intel® Quartus® Prime Standard Edition Handbook Volume 1 Design and Synthesis, page 255.
