What is the maximum downward pressure that can be applied to the top of Altera BGA packages?
Description The following guidelines refer to the downward pressure or compressive load that can be applied to the top of Altera® FPGA BGA packages. Pitch (mm) Pattern Package Type Constant Compressive Load per Solder Ball (g) Eutectic SnPb (tin-lead) SAC (tin-silver-copper) 0.5 Grid MBGA 3 7 0.8 Grid UBGA 6 12 0.92 Hex FBGA 7 14 1 Hex FBGA 8 15 1 Grid FBGA 8 16 1.27 Grid BGA 12 24 Resolution For heat-sink application, Altera recommends heat sink pressure on the package between 20psi to 40psi for effective Thermal Interface Material (TIM) performance Your PCB and the supporting frame should be designed to withstand the pressure of the downward force to prevent bending or flexing of your PCB.
Why does the text overlap in the ALTPLL IP Parameter Editor?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1, you might see that the text overlaps in the ALTPLL IP Parameter Editor on the Windows* Operating System. This prevents the ALTPLL IP from being instantiated. This problem does not occur in the Quartus® Prime Standard Edition Software version 24.1 and earlier. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 25.1, download and install the patch below: This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.Error: TBBmalloc: skip allocation functions replacement in ucrtbase.dll: unknown prologue for function _msize
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1 or earlier, you might see this error message when generating PLL IP on Windows* 11 Operating System. The IP generation might complete successfully even though this error message is reported. Resolution To work around this problem, follow these steps: Go to This PC, right-click, and select Properties. Click Advanced System Setting. In the Advanced tab, select Environment Variable. Under System variables, create a new variable with the name TBB_MALLOC_DISABLE_REPLACEMENT and value as 1. Click OK and restart the Quartus® Prime Software. The workaround above does not work for the Quartus® Prime Standard Edition Software version 22.1std.2 or earlier. A patch is available to fix this problem for the Quartus® Prime Standard Edition Software version 22.1std.2. The environment variable is still required to prevent the TBBmalloc message from appearing. Download and install patch 2.02 below: Patch 2.02 for Windows (.exe) Readme for patch 2.02 (.txt) This problem is not scheduled to be fixed in the Quartus® Prime Standard Edition Software.Error : FLEXlm version of vendor daemon is too old
Description In the Questa* FPGA Edition simulator and Questa* FPGA Starter Edition simulator version 2024.1, you might see this error or the following error if you are using the MGCLD daemon v11.16.4 “Unable to checkout a license. Make sure your license file environment variable (SALT_LICENSE_SERVER, MGLS_LICENSE_FILE, LM_LICENSE_FILE) is set correctly” Resolution To avoid this error, upgrade to the Siemens* Flexlm (SALTD) daemon v11.19.5 Download the daemon from the download page There is a change to the Siemens* License in v11.19.5.0. If you’re running a floating license server for Siemens* licenses, manually change the VENDOR daemon line in the license file from mgcld to saltd, for example: VENDOR saltd <path to saltd> Note: Do not change any of the INCREMENT lines. Leave the INCREMENT lines with the original vendor daemon name (mgcld).When does the Quartus® Prime Design Software, IP cores, and Questa*-Altera® FPGA Edition Software check out a license?
Description Below is a description of how the Quartus® Prime Design Software, IP cores, and Questa*-Altera® FPGA Edition Software utilize licenses: Resolution Quartus® Prime Design Software: All Quartus® Prime Design Software processes check for a valid license, including the Quartus® GUI, Analysis & Synthesis, Assembler, and TimeQuest Timing Analyzer. These processes start only if a valid license is available. They do not hold or occupy the license; they only validate that one is available. However, the Fitter checks out a license when it starts and holds it for the duration of the Fitter process. IP cores: A license for an IP core is checked out when the Quartus® Prime Design Software opens the first encrypted file of the IP core for synthesis. This license is held for the duration of synthesis. The Assembler checks out the license for every IP core to create the programming file and holds it for the duration of the Assembler process. Questa*-Intel® FPGA Edition software: Once Questa*-Intel® FPGA Edition Software loads a design unit during elaboration, a Questa-Intel® FPGA Edition license is checked out. It remains checked out until the simulation ends (quit -sim), or the simulator is closed. Once a waveform is loaded into the simulator, a Questa*-Intel® FPGA Edition Software license is also checked out for viewing Wave Log Format File (.wlf), and it remains checked out until the waveform window is closed. Related Articles What happens to a license if the Quartus II software terminates unexpectedly? Can I perform multiple compilations using the Quartus II software at the same time on one computer with a one seat floating license or one fixed (node locked) license file?How much can I expect the solder balls of a BGA package to shrink after reflow?
Description You can expect the solder balls of a BGA package to shrink by about a third after reflow. For example, if the solder balls have a height of 0.3mm before reflow, they will shrink to a height of about 0.2mm after reflow.How can I use command line (quartus_pgm) to program a CFI flash device via the Parallel Flash Loader (PFL) megafunction in a MAX II or MAX V CPLD?
Description To use the command line interface to program a CFI flash device via the Parallel Flash Loader (PFL) megafunction in a MAX® II or MAX® V device, follow the instructions below : 1. In Quartus® II Programmer, add the MAX device and CFI flash device you wish to program and then assign the PFL .pof and CFI flash .pof accordingly. 2. Save this as a Chain Description File (.cdf) file 3. In command line, use the following command to program the devices : quartus_pgm -c <cable index> filename.cdf To find out the cable index for your download cable, execute : jtagconfig -nHow do I program MAX® II, MAX® V, or Intel® MAX 10 devices with the real-time ISP feature using the quartus_jli command?
Description You can use a JAM STAPL Format File (.jam) file or Jam Byte Code (.jbc) file with the quartus_jli command to program a MAX® II, MAX® V, or Intel® MAX® 10 device with real-time ISP feature. Resolution To create a Jam or JBC file, follow these steps: Choose Programmer under the Tools menu in the Intel® Quartus® Prime Software, or start the stand-alone Programmer. Display the JTAG chain of your devices by clicking Auto Detect, opening the Chain Description File (.cdf) file or adding devices manually. Add your target Programmer Object File (.pof) to the MAX II, MAX V, or Intel MAX 10 device to program. For Intel MAX 10 devices, ensure the Enable real-time ISP to allow background programming when available option is selected. Choose Create JAM, JBC, SVF or ISC file under the File menu. Type a file name and a file path to store in File name box. Choose JEDEC STAPL Format (.jam) or Jam STAPL Byte Code 2.0 (.jbc) from the File format list. Click OK. To program the MAX II, MAX V, or Intel MAX 10 device using the Jam or JBC file with real-time ISP feature using quartus_jli, use the following commands respectively: For Jam file quartus_jli -aPROGRAM --enable=DO_REAL_TIME_ISP <file name>.jam For JBC file quartus_jli -aPROGRAM --enable=DO_REAL_TIME_ISP <file name>.jbc Related Articles How do I enable the real-time ISP feature in the Quartus® II Programmer or Jam/JBC to allow a MAX® II device to continue to run in-system while new programming data is loaded into the configuration flash memory (CFM)?How to mitigate the security vulnerability in the Nios® II Command Shell utility?
Description Due to a problem in the Quartus ® Prime Standard and Lite Edition Software version 19.1 through 24.1, the Nios® II Command Shell utility included in the Quartus ® Prime Software for Windows* is vulnerable to a Current Working Directory (CWD) planting attack. The Linux* versions are not affected. Resolution To work around this problem, replace the “Nios II Command Shell.bat” Windows Batch File located in the <drive>:\<edition>\<version number>\nios2eds\, with the attached file below. This problem is fixed beginning with the Quartus® Prime Standard and Lite Edition Software version 25.1.Why does Nios® V processor design fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus® Prime project instead of the QIP file?
Description In the Quartus ® Prime Standard Edition software version 25.1, any Nios ® V processor designs might fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus ® Prime project. Here are the possible error messages that you might receive: Error (10170): Verilog HDL syntax error at niosv_cpp_fsm.sv(1418) near text: "'"; expecting ":", or "?", or binary operator. Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2) Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions Error (16950): Verilog HDL error at : decimal constant 00000000000000010000000000000000 is too large, using 1874919424 instead Error (16814): Verilog HDL error at ... : unknown literal value 00000000000000010000000000000000 for parameter ... ignored This is because the Quartus ® Prime Standard Edition software version 25.1 has been updated to adhere to the software requirements below. This requirement is not mandatory in prior versions of the Quartus ® Prime Standard Edition software. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, Remove the QSYS file from the project using the Remove Files in Project function. Add the QIP file to the project using the Add Files in Project function. Related Articles ERROR building simple NIOS® V Compact project Nios® V Synthesis Fails with Quartus® Prime 25.1 Lite
