Why does the text overlap in the ALTPLL IP Parameter Editor?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1, you might see that the text overlaps in the ALTPLL IP Parameter Editor on the Windows* Operating System. This prevents the ALTPLL IP from being instantiated. This problem does not occur in the Quartus® Prime Standard Edition Software version 24.1 and earlier. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 25.1, download and install the patch below: This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.Why does Ashling* RiscFree* IDE for Altera® FPGAs detect Core 0 only in a Nios® V processor multicore system?
Description Due to a problem in the Ashling* RiscFree* IDE for Altera software version 25.2.1 (version dated 9 th May 2025), the Ashling* RiscFree* IDE might fail to detect other Nios ® V processor cores (except Core 0) for Nios ® V processor multicore designs. This is because there is a bug in the Ashling* GDBServer software. Error message: [GDB server output] Error: The device configuration selected has only 1 core (Core 0). Core 1 is not available. Resolution To workaround this issue, please switch from Ashling* GDBServer to Open On-Chip Debugger (OpenOCD) when debugging a Nios ® V multicore processor system. Add the “–o" argument when running niosv-download. niosv-download app.elf -o <options> The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.
What is the maximum downward pressure that can be applied to the top of Altera BGA packages?
Description The following guidelines refer to the downward pressure or compressive load that can be applied to the top of Altera® FPGA BGA packages. Pitch (mm) Pattern Package Type Constant Compressive Load per Solder Ball (g) Eutectic SnPb (tin-lead) SAC (tin-silver-copper) 0.5 Grid MBGA 3 7 0.8 Grid UBGA 6 12 0.92 Hex FBGA 7 14 1 Hex FBGA 8 15 1 Grid FBGA 8 16 1.27 Grid BGA 12 24 Resolution For heat-sink application, Altera recommends heat sink pressure on the package between 20psi to 40psi for effective Thermal Interface Material (TIM) performance Your PCB and the supporting frame should be designed to withstand the pressure of the downward force to prevent bending or flexing of your PCB.Error: TBBmalloc: skip allocation functions replacement in ucrtbase.dll: unknown prologue for function _msize
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1 or earlier, you might see this error message when generating PLL IP on Windows* 11 Operating System. The IP generation might complete successfully even though this error message is reported. Resolution To work around this problem, follow these steps: Go to This PC, right-click, and select Properties. Click Advanced System Setting. In the Advanced tab, select Environment Variable. Under System variables, create a new variable with the name TBB_MALLOC_DISABLE_REPLACEMENT and value as 1. Click OK and restart the Quartus® Prime Software. The workaround above does not work for the Quartus® Prime Standard Edition Software version 22.1std.2 or earlier. A patch is available to fix this problem for the Quartus® Prime Standard Edition Software version 22.1std.2. The environment variable is still required to prevent the TBBmalloc message from appearing. Download and install patch 2.02 below: Patch 2.02 for Windows (.exe) Readme for patch 2.02 (.txt) This problem is not scheduled to be fixed in the Quartus® Prime Standard Edition Software.