JESD240B - No license
Hi, I am running the ADC on the Arrow DevKit – Agilex 5 E-Series AXE5 Eagle Development Platform. The converter is the EVAL-AD9695, which uses the JESD204B interface. I initially used ‘Generate Example Design’ and then adapted it for this converter. However, after making the changes and assigning the pins, I wanted to generate the final output file, but I encountered the following license error: On the licensing page, I do not see any entry for JESD204B anywhere. “What can I do to test the design? I previously worked with the Arria 10 GX, and I did not have such problems there.
Max 10 Jtag secure mode issues for lock/unlock jtag
Hi All, I am reviewing the doc for MAX 10 JTAG Secure Mode. https://www.intel.com/content/www/us/en/docs/programmable/683865/current/fpga-configuration-overview.html page 58 with topic 3.9 I am still not clear about steps which shown to lock and unlock jtag with the example design. I have following questions. 1. JTAG WYSIWYG atom is IP? how to instantiate directly with my design? where is this design in fpga? 2. Where to get this signals start_lock, start_unlock, indicator, counter_output ? how to update it at run time? is there any tool to support it?3. Still uncleared picture of how to update and based on what? 3. how to lock jtag? is it icb settings only? 4. Is there any use of jtag unique id or key for secure mode? Hope to get asap response. Thanks,
Agilex 7 LVDS SERDES IP : Wrong behavior in simulation (coreclock too slow)
Hello, I've been trying to simulate the LVDS SERDES IP (6-bit) on my design with Questa Intel FE, and it looks like there is something weird with the coreclock output (both in TX and RX). I see the same problem either in internal or external PLL modes. In addition, I have generated the Example Design, and the problem persists (of course, the testbench checker fails). The issue is that the coreclock is about 30 times slower than expected. Here you can find some screenshots: 1) Initially, the ext_lvds_clk is a slow clock. In this case, ext_loaden is triggered every 6 cycles, and tx_coreclock is coherent too. But then the ext_lvds_clk switches to the fast clock, and we can see that ext_loaden remains coherent to that clock, but tx_coreclock doesn't. 2) Looking more in detail, we can see that coreclock remains low for 3 cycles (that's correct), but it remains high for many more cycles than 3. In consequence, most of the input samples are skipped. 3) The same situation persists once the SERDES IP locks. As a result, the same input word is serialized several times over and over again for each coreclock cycle. For information, I'm using Quartus Prime Edition 24.3 Is there anything I'm doing wrong? Thanks in advance! Jaime
JESD204B Latency Issue – Sample Shift Observed
Hi All, We are using a JESD204B IP core (Subclass 1) to receive trigger-synchronized data from an ADC. After every power cycle or reconfiguration, the lane alignment results in different latency. After each power cycle or reconfiguration, we observe a shift in the ADC samples. Sometimes it's 1 sample, sometimes 3, and it can go up to 8 samples. I hope someone can help me with this issue to find out potential causes for this behavior and suggest ways to resolve or mitigate it? Can we know this latency, how to reduce this latency. Setup: JESD204B Configuration: L=4, M=1, F=2, S=4 and K=16. Subclass 1 with continuous SYSREF. The IOPLL compensation mode is set to "source synchronous"
JESD204C - Reconfig XCVR Register Access
We are attempting to access the JESD XCVR Reconfiguration registers via the HPS H2F interface. We are able to successfully read from and write to the intended addresses. However, instead of receiving the full 16-bit readdata, we are consistently observing only an 8-bit readdata being returned from the JESD IP. Please note that both JESD TX CSR and RX CSR Register accesses through HPS LW bridge were working as expected. Brief description of the code snippets attached: Register write to address 0x9003C Register read from address 0x90040 Regardless of the register writes, we always receive the readdata as 0x65 Register description for these registers were not available in IP user Guide or in Register map document. Could anyone please provide or point us to the documentation or details related to the JESD Reconfig XCVR registers? This would help us better understand the expected behavior and usage.Direct RF IP
We have a Stratix 10AX development kit and am trying to get setup to start developing with it. I am setup with access to the RDC and have downloaded the documentation, it says about installing the Direct RF IP but I can only see the Linux version in the RDC, is there a Windows version of the IP patch or do I have to install the tools under Linux?
Direct RF Transceiver Intel FPGA IP in Stratix 10 AX
Hi, I am currently working with an FPGA Stratix 10 AX chip (1SA28T) and attempting to build a project using Quartus 22.3. However, I am encountering an error indicating that the drf_xcvr IP component is missing. Upon further internet investigation and using QSYS, I found that this IP is referred to as "Direct RF Transceiver FPGA Intel IP." I would appreciate any information regarding this IP, including whether it is available for download or how I can obtain access to it. Any support on this matter would be greatly appreciated.Intel Agilex 7 FPGA E-Tile Transceiver PHY - Parallel Data
Hi everyone, I have doubt in the parallel data interface of Intel Agilex 7 FPGA's E-Tile Transceiver PHY IP core. My design has a parallel data of 128-bit width, So I used the "Enable TX/RX double width transfer" option. I referred the 'E-Tile Transceiver PHY User Guide (UG-20056)' about the connectivity of parallel data using double width transfer. It seems that the TX/RX parallel data ports of the Transceiver are 80-bit wide, but the Table 32. in the user guide shows connectivity of 160-bit wide data. I've attached the snapshot for your reference. Please help to clarify my doubt and to integrate my design with the Transceiver. Thanks in advance, ArunAD9082 EVM -Stratix10 EDK JESD204B Link Up Issues
Hi, I got Stuck with ad9082 adc path in which jesd link up is not coming up! am getting kchar, disparity errors , but in the same design DAC is working ! I have forced the rx_sync signal from jesd ip side to ad9082 jesd tx (ADC) to identify the issue ,In this case status passed to UDATA from CGS.I have attached the logs and signal tap files for your reference. But In normal working case sync is always low and still I am getting kchar , disparity errors. I have taken an example design for reference and testing. With jesd(duplex) ip ,DAC link is fine but ADC link is not responding! Please help us to resolve this. I don't know what exactly the issue is ! whether ad9082 K char transmission or JESD RX IP receiving!! Got stuck at this issue for a long time !! please help me to resolve this!!!!! I am observing same behavior in Stratix10 and Arria10 Dev kits. Usually Clock for ADC is generated by DAC with some divider values. Here I am using Duplex ip in which both jesd Transmitter and receiver are mixed ,so same clock for both in FPGA side. with the same clock frequency and levels ,DAC is working fine ! Do ADC clock need any extra power level compared to DAC clock power level ? Thanks In Advance!! @jesd204b
Cyclone 10 GX transceiver RX word align pattern
Hello, I am using the Cyclone 10 GX transceiver, and wanted to try out synchronous state machine word alignment in simulation for now. I set the RX word aligner pattern to 0x17C, 10 bits. I enabled 8b10b coding on both RX and TX. I am then sending 0xBCBC control characters. I would expect the RX to synchronize to the TX word, and get pattern matches. But it never does, and I get no pattern matches. I tried also putting in data between the control K28.5 characters. But that hasn't helped either. I've also tried bitslip instead of synchronous state machine, and it worked just fine, I could send a few bitslips to sync to TX. Am I doing something wrong? What could be the problem? I am attaching a screenshot with this behavior, I can send more if needed.
