Max 10 Jtag secure mode issues for lock/unlock jtag
Hi All, I am reviewing the doc for MAX 10 JTAG Secure Mode. https://www.intel.com/content/www/us/en/docs/programmable/683865/current/fpga-configuration-overview.html page 58 with topic 3.9 I am still not clear about steps which shown to lock and unlock jtag with the example design. I have following questions. 1. JTAG WYSIWYG atom is IP? how to instantiate directly with my design? where is this design in fpga? 2. Where to get this signals start_lock, start_unlock, indicator, counter_output ? how to update it at run time? is there any tool to support it?3. Still uncleared picture of how to update and based on what? 3. how to lock jtag? is it icb settings only? 4. Is there any use of jtag unique id or key for secure mode? Hope to get asap response. Thanks,
AD9082 EVM -Stratix10 EDK JESD204B Link Up Issues
Hi, I got Stuck with ad9082 adc path in which jesd link up is not coming up! am getting kchar, disparity errors , but in the same design DAC is working ! I have forced the rx_sync signal from jesd ip side to ad9082 jesd tx (ADC) to identify the issue ,In this case status passed to UDATA from CGS.I have attached the logs and signal tap files for your reference. But In normal working case sync is always low and still I am getting kchar , disparity errors. I have taken an example design for reference and testing. With jesd(duplex) ip ,DAC link is fine but ADC link is not responding! Please help us to resolve this. I don't know what exactly the issue is ! whether ad9082 K char transmission or JESD RX IP receiving!! Got stuck at this issue for a long time !! please help me to resolve this!!!!! I am observing same behavior in Stratix10 and Arria10 Dev kits. Usually Clock for ADC is generated by DAC with some divider values. Here I am using Duplex ip in which both jesd Transmitter and receiver are mixed ,so same clock for both in FPGA side. with the same clock frequency and levels ,DAC is working fine ! Do ADC clock need any extra power level compared to DAC clock power level ? Thanks In Advance!! @jesd204b
JESD Test Bench Simulation - no activity
Hello I am using Quartus Prime Pro 22.4.0 on Windows and Questa Intel Starter FPGA-64 2022.1 on Windows. The full path to my project is: c:/jesd and the project name is also "jesd". The JESD204B IP that I created is called "my_j" and so the testbench resides at default directory: c:/jesd/my_j_tb The generation of HDL and Test-Bench from within the IP Parameter Editor was OK. Note that I have configured JESD to match my specific board requirements. Within Questa I am changing to directory: c:/jesd/my_j_tb/my_j_tb/sim/mentor and sourcing msim_setup.tcl This proceeds to compile and elaborate without any errors. However, when I run the simulation, there is no activity on any signals with the except of clocks and resets. What am I doing wrong? Thank you for any answers.
JESD204B disassembler
Follow up questions after this post: https://community.intel.com/t5/forums/forumtopicpage/board-id/fpga-intellectual-property/message-id/27524#M27524 I know that the TL is not part of the core IP and that I must implement this. Note that the example design does NOT cover my specific case of F=1, L=4, N=8, N'=8, M=4, S=1. I am asking how the received data is organized within the 128 bits parallel output of the core (rx_link_data). - for example, is it just simply 32 bits for each LANE? The reason I need this answer is so that I can write my own transport layer and de-assembler code. A few additional questions are: I am using 10 identical cores with parameters as above. (Therefore I am using a total of 40 GXB Receivers). The 10 identical ADC devices (each with M=4) are clocked synchronously from a central clock generator, although I do NOT require synchronous sampling. The sample rate is 500 MSPS, meaning the line rate on each lane is 5G. Is it sufficient to use a single core PLL within Arria 10 to supply the device_clk, link_clk and frame_clk to all 10 instantiations of the core IP? This core PLL will have its reference synchronous to the JESD204 data stream of course. Do you recommend Hard or Soft PCS for this case? Any other recommendations for my specific case?Request for an official email to declare Intel acquired structured eASIC company.
Our company want to send an quotation to eASIC company before, but found that Intel acquired structured ASIC company eASIC into Programmable Systems Group (PSG). Could you please send us an official email to declare this situation for our record, thank you.
Cyclone 10 GX transceiver RX word align pattern
Hello, I am using the Cyclone 10 GX transceiver, and wanted to try out synchronous state machine word alignment in simulation for now. I set the RX word aligner pattern to 0x17C, 10 bits. I enabled 8b10b coding on both RX and TX. I am then sending 0xBCBC control characters. I would expect the RX to synchronize to the TX word, and get pattern matches. But it never does, and I get no pattern matches. I tried also putting in data between the control K28.5 characters. But that hasn't helped either. I've also tried bitslip instead of synchronous state machine, and it worked just fine, I could send a few bitslips to sync to TX. Am I doing something wrong? What could be the problem? I am attaching a screenshot with this behavior, I can send more if needed.INTEL IP JESD204B information
Hi All, We're currently developing a project and we need to interface our Arria10 SoC to a AD9174 through JESD204B. We are interested in using the Intel IP for the JESD204B and I have a few questions. Out application wants to use the AD9174 in mode 9 and dual link, this means that of the 8 total lanes of the device, 4 are dedicated to one link and 4 to the other. In the current solution we are setting one link to work (using the 4 lanes) but we cannot make the other to work since the second 4 transceivers are distributed in 2 different banks (two are together with the first 4 lanes while the other 2 are in the different bank) for this reason, the fitter cannot synthesize correctly the design since there is no option to bond the clocks between the 2 pair of transceivers. Does the JESD204B IP from Intel solves this problem? Thanks and best regards, Marco
Whether legacy epcs/epcq serial flash controller can be used in design 22.1 version quartus tool
Hi team, I am upgrading the design from 13.1 to 22.1 version tool, in that design legacy epcs/epcq serial flash controller is used. I am retaining that legacy ip and using it. can i use that for configuring epcq devices? if not please provide suggestionsAgilex 7 LVDS SERDES IP : Wrong behavior in simulation (coreclock too slow)
Hello, I've been trying to simulate the LVDS SERDES IP (6-bit) on my design with Questa Intel FE, and it looks like there is something weird with the coreclock output (both in TX and RX). I see the same problem either in internal or external PLL modes. In addition, I have generated the Example Design, and the problem persists (of course, the testbench checker fails). The issue is that the coreclock is about 30 times slower than expected. Here you can find some screenshots: 1) Initially, the ext_lvds_clk is a slow clock. In this case, ext_loaden is triggered every 6 cycles, and tx_coreclock is coherent too. But then the ext_lvds_clk switches to the fast clock, and we can see that ext_loaden remains coherent to that clock, but tx_coreclock doesn't. 2) Looking more in detail, we can see that coreclock remains low for 3 cycles (that's correct), but it remains high for many more cycles than 3. In consequence, most of the input samples are skipped. 3) The same situation persists once the SERDES IP locks. As a result, the same input word is serialized several times over and over again for each coreclock cycle. For information, I'm using Quartus Prime Edition 24.3 Is there anything I'm doing wrong? Thanks in advance! Jaime
