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VenkateshK's avatar
VenkateshK
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

AD9082 EVM -Stratix10 EDK JESD204B Link Up Issues

Hi,
I got Stuck with ad9082 adc path in which jesd link up is not coming up! am getting kchar, disparity errors , but in the same design DAC is working !
I have forced the rx_sync signal from jesd ip side to ad9082 jesd tx (ADC) to identify the issue ,In this case status passed to UDATA from CGS.I have attached the logs and signal tap files for your reference.
But In normal working case sync is always low and still I am getting kchar , disparity errors. I have taken an example design for reference and testing. With jesd(duplex) ip ,DAC link is fine but ADC link is not responding! Please help us to resolve this.
I don't know what exactly the issue is ! whether ad9082 K char transmission or JESD RX IP receiving!!
Got stuck at this issue for a long time !! please help me to resolve this!!!!!
I am observing same behavior in Stratix10 and Arria10 Dev kits.
Usually Clock for ADC is generated by DAC with some divider values. Here I am using Duplex ip in which both jesd Transmitter and receiver are mixed ,so same clock for both in FPGA side. with the same clock frequency and levels ,DAC is working fine !
Do ADC clock need any extra power level compared to DAC clock power level ?
Thanks In Advance!!
@jesd204b
Jesd

7 Replies

  • ZH_Intel's avatar
    ZH_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi VenkateshK,


    Thank you for reaching out.

    Just to let you know that Intel has received your support request and I am assigned to work on it.

    Allow me some time to look into your issue. I shall come back to you with findings.


    Thank you for your patience.

    Best Regards,

    ZH_Intel


    • VenkateshK's avatar
      VenkateshK
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Dear sir,

      Any update on this issue, Please help us to resolve this issue, we are struggling from long time.

  • ZH_Intel's avatar
    ZH_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi VenkateshK,


    Apologize for the delayed response as we encounter some technical difficulty.

    Could you share with me, what clock are you giving for the design? (device clock, core clock and sysclk)


    Thank you.

    Best Regards,

    ZH_Intel



  • ZH_Intel's avatar
    ZH_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi VenkateshK,


    Good day.

    I wish to follow up with you on this Case.

    I would like to get update on my previous reply.

    Could you share with me, what clock are you giving for the design? (device clock, core clock and sysclk)


    Thank you.

    Best Regards,

    ZH_Intel


  • ZH_Intel's avatar
    ZH_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi VenkateshK,


    Good day.

    Since we do not receive any response from you for quite some time to the previous reply that I have provided.

    This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


    Thank you.

    Best Regards,

    ZH_Intel


  • VenkateshK's avatar
    VenkateshK
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Thank you.

    Issue is resolved on Strati10 Dev kit as it is encoding issue at converter side.