INTEL IP JESD204B information

Question

Hi All,We're currently developing a project and we need to interface our Arria10 SoC to a AD9174 through JESD204B. We are interested in using the Intel IP for the JESD204B and I have a few questions.Out application wants to use the AD9174 in mode 9 and dual link, this means that of the 8 total lanes of the device, 4 are dedicated to one link and 4 to the other. In the current solution we are setting one link to work (using the 4 lanes) but we cannot make the other to work since the second 4 transceivers are distributed in 2 different banks (two are together with the first 4 lanes while the other 2 are in the different bank) for this reason, the fitter cannot synthesize correctly the design since there is no option to bond the clocks between the 2 pair of transceivers.Does the JESD204B IP from Intel solves this problem?Thanks and best regards,Marco

zh_intel · Answer

Hi Marco,Thank you for reaching out.Apologize for the delayed response as we encounter some technical difficulty.Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.I shall come back to you with findings.Thank you for your patience.Best Regards,ZulsyafiqH_Intel

zh_intel · Answer

Hi Marco,Thank you for your patience.Allow me to clarify with you on my understanding, you trying to create an Interop design(JESD204B IP with converter)?Based on our records, there are no reference that uses AD9174 interface with Arria 10 device.However we do have an application note that uses AD9174 with Stratix 10 device that you can refer to as reference.AN 890: JESD204B Intel® FPGA IP and ADI AD9174 Interoperability Report for Intel Stratix® 10 L-Tile Devices We also have other documentation that I think might be useful for you:AN 803: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide Thank you.Best Regards,ZulsyafiqH_Intel

zh_intel · Answer

Hi Marco,We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.Thank you.Best Regards,ZulsyafiqH_Intel

Forum Discussion

INTEL IP JESD204B information

3 Replies

Recent Discussions

About Design Limitations and Known Issues

About Dual Simplex for Agilex 3

Where is High Speed Transceiver Demo Design in FPGA Wiki ?

Can't find Agilex 7 M I/O PLL Reconfiguration Design Example

Enabling DFE Adaptation on Cyclone 10 GX