Forum Discussion

bbT's avatar
bbT
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

JESD204B disassembler

Follow up questions after this post:

https://community.intel.com/t5/forums/forumtopicpage/board-id/fpga-intellectual-property/message-id/27524#M27524

I know that the TL is not part of the core IP and that I must implement this.
Note that the example design does NOT cover my specific case of F=1, L=4, N=8, N'=8, M=4, S=1.
I am asking how the received data is organized within the 128 bits parallel output of the core (rx_link_data).
- for example, is it just simply 32 bits for each LANE?
The reason I need this answer is so that I can write my own transport layer and de-assembler code.
A few additional questions are:
I am using 10 identical cores with parameters as above.
(Therefore I am using a total of 40 GXB Receivers).
The 10 identical ADC devices (each with M=4) are clocked synchronously from a central clock generator, although I do NOT require synchronous sampling.
The sample rate is 500 MSPS, meaning the line rate on each lane is 5G.
Is it sufficient to use a single core PLL within Arria 10 to supply the device_clk, link_clk and frame_clk to all 10 instantiations of the core IP?
This core PLL will have its reference synchronous to the JESD204 data stream of course.
Do you recommend Hard or Soft PCS for this case?
Any other recommendations for my specific case?
Jesd

6 Replies

  • David32's avatar
    David32
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hi all,

    Thank you in advance for anyone who can provide some answers to the above questions.

    David

  • ZH_Intel's avatar
    ZH_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi there,

    Thank you for reaching out.

    Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

    I shall come back to you with findings.

    Thank you for your patience.

    Best Regards,

    ZulsyafiqH_Intel


  • David32's avatar
    David32
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    I am adding another question.

    Can I swap between the 4 lanes in a single link in order to make routing on the board easier.

    Thanks

    David

  • ZH_Intel's avatar
    ZH_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi David,


    Apologize for the delayed response as we encounter some technical difficulty.

    I think you can identify byte(octet) order in parallel data and how to re-arrange once you would run simulation with example design even it is S=16.

    I believe my collogue skbeh has already provide this answer.


    The point we need to pay attention is octet(byte) is MSB first, but the transceiver is LSB first.

    You can see it in the example design.


    Thank you.

    Best Regards,

    ZH_Intel


  • ZH_Intel's avatar
    ZH_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi David,


    Good day.

    Do you still have further inquiries?

    If there is no further inquiries, I will transition this thread to community support.


    Thank you.

    Best Regards,

    ZH_Intel


  • ZH_Intel's avatar
    ZH_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi David,


    We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


    Thank you.

    Best Regards,

    ZH_Intel