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New ContributorJESD204B disassembler
Follow up questions after this post:
I know that the TL is not part of the core IP and that I must implement this.
Note that the example design does NOT cover my specific case of F=1, L=4, N=8, N'=8, M=4, S=1.
I am asking how the received data is organized within the 128 bits parallel output of the core (rx_link_data).
- for example, is it just simply 32 bits for each LANE?
The reason I need this answer is so that I can write my own transport layer and de-assembler code.
A few additional questions are:
I am using 10 identical cores with parameters as above.
(Therefore I am using a total of 40 GXB Receivers).
The 10 identical ADC devices (each with M=4) are clocked synchronously from a central clock generator, although I do NOT require synchronous sampling.
The sample rate is 500 MSPS, meaning the line rate on each lane is 5G.
Is it sufficient to use a single core PLL within Arria 10 to supply the device_clk, link_clk and frame_clk to all 10 instantiations of the core IP?
This core PLL will have its reference synchronous to the JESD204 data stream of course.
Do you recommend Hard or Soft PCS for this case?
Any other recommendations for my specific case?
