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bbT's avatar
bbT
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

JESD204B disassembler

Follow up questions after this post: https://community.intel.com/t5/forums/forumtopicpage/board-id/fpga-intellectual-property/message-id/27524#M27524 I know that the TL is not part of the core ...
Jesd
ZH_Intel's avatar
ZH_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi David,


Apologize for the delayed response as we encounter some technical difficulty.

I think you can identify byte(octet) order in parallel data and how to re-arrange once you would run simulation with example design even it is S=16.

I believe my collogue skbeh has already provide this answer.


The point we need to pay attention is octet(byte) is MSB first, but the transceiver is LSB first.

You can see it in the example design.


Thank you.

Best Regards,

ZH_Intel