JESD204B Latency Issue – Sample Shift Observed

Hi All,

We are using a JESD204B IP core (Subclass 1) to receive trigger-synchronized data from an ADC. After every power cycle or reconfiguration, the lane alignment results in different latency.

After each power cycle or reconfiguration, we observe a shift in the ADC samples. Sometimes it's 1 sample, sometimes 3, and it can go up to 8 samples.

I hope someone can help me with this issue to find out potential causes for this behavior and suggest ways to resolve or mitigate it? Can we know this latency, how to reduce this latency.

Setup:

JESD204B Configuration:

L=4, M=1, F=2, S=4 and K=16.

Subclass 1 with continuous SYSREF.

The IOPLL compensation mode is set to "source synchronous"