RongY_altera
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Re: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
I was not aware of this is a RP use case so my previous suggestions were not aligned to your needs. I noticed you have another similar topic in the forum with better statement. https://community.altera.com/discussions/fpga-device/avalon-mm-cyclone-v-hard-ip-for-pci-express-intel-fpga-ip---hard-reset-to-soft-r/350590 To prevent duplicate threads on the same issue, this topic will be closed. Thanks for your understanding. Regards, Rong16Views0likes0CommentsRe: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
"Once confirming PCIe link info correctly in lspci, you can try rescan and reset commands by referencing https://unix.stackexchange.com/questions/73908/how-to-reset-cycle-power-to-a-pcie-device" >>These are Linux commands to test your PCIe. No need to load driver. Regards, Rong21Views0likes2CommentsRe: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
Normally you need to follow the PCIe user guide to set hip_hard_reset_hwtcl to 0. I think you have done that and you're able to boot into Linux. Once confirming PCIe link info correctly in lspci, you can try rescan and reset commands by referencing https://unix.stackexchange.com/questions/73908/how-to-reset-cycle-power-to-a-pcie-device Regards, Rong17Views0likes4CommentsRe: agilex 7 Platform Designer PIO addr width
After you expand the BAR0 size, you'll need to expand some related modules inside PCIe PIO as well if you really need 2M size. if you'd like to check, a performance design like DMA doesn't always require a large BAR0. The way to use on-chip ram is important. Since the PIO module does the AVST to AVMM transformation, here are some places I think you can try. Below filenames could be different from yours. After the completion of Synthesis, you can find below module in ip/pcie_ed/pcie_ed_pio0/synth/pcie_ed_pio.v. You may increase the PIPELINE_EN to a larger number. This file ip/pcie_ed/intel_pcie_pio_g4_2431/synth/intel_pcie_bam_sch_intf_pipeline.sv does HIP to AVMM conversion. Right there, you can find a 16KB FIFO here. I think you need to expand both read and write FIFOs for a larger amount of data. Regards, Rong1View1like0CommentsRe: agilex 7 Platform Designer PIO addr width
Hi, AVMM is no longer used in PCIe example designs. If you still want to use PCIe+AVMM, you can upgrade your original design to a newer Quartus. If you want to try PCIe+AVST and have problem in using the BAR0, please let me know your Quartus version. Regards, Rong11Views0likes3CommentsRe: Agilex 7 R-Tile RES FPGA – CXL Device Enumeration Failure with CXL IP Design Example
I've tried few older versions, even Quartus 22.4 Pro generates example design for AGIB027R29A1E2VR3, not for AGIB027R29A1E2VR0. Using an old example design is not recommended since it may contain some known issues. I suggest you to generate an example design for DK-DEV-AGI027R1BES. It's also power solution 1. Then modify OPN and necessary settings for DK-DEV-AGI027RES. Regards, Rong11Views0likes0CommentsRe: Agilex 7 R-Tile CXL Type-2 IP Hang with Incomplete CXL.cache Operations
Hi, So far I don't see a known issue directly related to this. For such situation, I suggest you to check Channel Crediting section in the CXL spec and monitor corresponding credit count in the design. Regards, Rong29Views0likes1Comment