RongY_altera
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Re: PCIe reset stuck on Arrow Eagle board
Hi, According to the pin connection guide, the unused PERST pin for the same GTS bank must be left floating. Your PIN_CF132 and PIN_BU109 are on bank 5A and 5B, respectively. You may check the remaining PERST pins on these two banks. Regards, Rong268Views0likes1CommentRe: Agilex 5 FPGAs compatible with external optical transceiver
Hi Shmuel, Depends on your needs. For example, if you're planning a 40GE env, you can find the IP features here 1.1. Low Latency 40G Ethernet Intel® FPGA IP Supported Features and supported FPGA here 1.2.1. Low Latency 40G Ethernet Intel® FPGA IP Device Family Support Besides of these, you can create an example design and check IP settings to make sure it can enable some extra feature you may want in the future. You can find a comparison here. For example, if 1588 PTP is required, you may need to check Agilex 7 F-Tille. 8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs Regards, Rong68Views0likes0CommentsRe: 1000Base-KX support in Arria V/10
Hi, The 10GBASE-KR PHY is protocol-specific. https://www.intel.com/content/www/us/en/docs/programmable/683171/current/protocol-specific-transceiver-phys.html For Arria 10, please refer to 10GBASE-KR PHY IP. 2.6.3. 10GBASE-KR PHY IP Core Regards, Rong77Views0likes0CommentsRe: Agilex 5 FPGAs compatible with external optical transceiver
Hi, You can find Agilex 5 GTS Eth Hard IP intro at below website. https://www.intel.com/content/www/us/en/products/details/fpga/intellectual-property/interface-protocols/gts-ethernet-hard-ip.html#tab-blade-1-0 And supported Eth IPs here. https://www.intel.com/content/www/us/en/docs/programmable/817676/25-1-1/ethernet-portfolio-and-target-applications.html It is hard to conclude which optical transceiver module would interoperate due to any mismatch between FPGA IP configuration and module capability will cause link failure. You may contact your local DFAE to help the selection. Regards, Rong223Views0likes1Comment