User Profile
RongY_altera
ContributorJoined 2 years ago
User Widgets
Contributions
Re: DK-DEV-AGI027RBES CXL Type-3 example remains in reset and is not detected by host
Hi Jeffrey, Since you've already tried PCIe ED, I think you have no problem in generating the CXL project. Based on the CXL UG for Q25.1.1, these steps are described in below chapters: 3. Generating the Design Example 5. Compiling the Design Example 6. Running the Design Example in Hardware Setup Pls notice you'll need to program the flash by following "6.3. Programming Agilex 7 I-Series Development Kit Image". Some details can also be found in this KDB. Make sure the dev kit switch is set to boot from flash. After the flash is programmed, do a cold reboot of the sever. Regards, Rong0Views0likes0CommentsRe: Fail to enumerate RTile PCIe in the AVSTx8 configuration
The OFS design is able to detect the PCIe device and perform testing successfully in the AVST configuration on the same hardware. >>The same hardware means the same dev kit or the same FPGA device? The Agilex7 I-series dev kit supports AVST x8 for sure. If you're using the same FPGA device on a different board, you need to check the board schematic to make sure. If the design partition you mentioned is CvP, I wonder how you create an image for the flash. Regards, Rong7Views0likes0CommentsRe: Terasic P16E-FMCP PCIE Express 3.0 compatibility issues with AMD processors
I don't have access to the Terasic application. From your description, the diagnostic tool reports that the PCIe read/write test passes. However, when you perform a manual single-step read/write test on the same design, the readback data does not match the data written. can you elaborate how I'm supposed to debug and querry the LTSSM state? >>You can ref doc here https://docs.altera.com/r/docs/683819/26.1/quartus-prime-pro-edition-user-guide/signal-tap-logic-analyzer-introduction 1. Create a Signal Tap (.stp) file. 2. Use the PCIe core clock (coreclkout_hip or equivalent) as the sampling clock. 3. Add the PCIe LTSSM status signal to Signal Tap. 4. Compile the design with Signal Tap enabled. With the stp, you can also monitor on chip mem read/write/address/data/valid signals to better understand how the application accesses mem and where the data mismatch occurs. Regards, Rong5Views0likes0CommentsRe: Fail to enumerate RTile PCIe in the AVSTx8 configuration
Hi Divya, Whether to use AVST x8 or AS x4 depends on how the FPGA is connected to the external configuration flash. You can verify this from the board schematic and then select the corresponding configuration scheme in your Quartus project. Based on the information you provided, your FPGA appears to be connected using the traditional Active Serial (AS x4) interface. Regards, Rong167Views0likes2CommentsRe: Terasic P16E-FMCP PCIE Express 3.0 compatibility issues with AMD processors
Since you have PCIe connection and can do a single byte operation to LEDs, this means the link and driver should be fine. Pls provide your lspci info for check. You can replace the PIO in your design with an on-chip mem to see if the read/write still works. Regards, Rong29Views0likes0CommentsRe: Agilex7 M PCIe MCDMA: debug toolkit attachment
Hi Ju-Ti, You need to get Quartus work first. Otherwise, the generated example might be incomplete. The M-series dev kit has 2x MCIO from R-Tile, and 1x FMC from F-Tile. The Q25.3.1 Pro I'm using can generate MCDMA example design for the R-Tile on the Agilex7 I-series dev kit. For a simple test, you can choose "PIO using MCDMA Bypass" design. After a successful compilation, you can start to migrate the design to the M-series dev kit. If you want a jtag master to control the p0_hip_reconfig, you can connect them in the qsys, and comment/remove virtual pins in the qsf. The MCDMA supports several user modes. Some signals may not be enabled in the selected mode. Regards, Rong24Views0likes1CommentRe: Agilex 7 R-Tile PCIe Gen5: Avalon-ST DMA MWr TLP accepted by HIP but never received by Root Port
Hi Reza, If the RP is a CPU-based server, you'll needs to allocate a mem space for FPGA to write to. The mem space has a physical address and OS manages virtual address. Your MWr writes to the physical address. When doing a print at the server side, you'll see virtual address is used. Regards, Rong45Views0likes0Comments