ContributionsMost RecentMost LikesSolutionsRe: R_Tile PCIE I modified the sim to repeatedly do read after write 100 times with increased data and saw no problem. If you do 100 128-byte data in a batch, you need to confirm sufficient size of mem has been reserved for your test. Regards, Rong Re: R_Tile PCIE Hi, Are you able to elaborate which part/file you've modified for the test? Regards, Rong Re: Why AXI MCDMA IP output axi-stream with Spares TKeep and borken TData? Hi, According to the spec, TKeep should be all ones for all non-TLAST cycles. The observed sparse TKeep before TLast violates this requirement. Please re-check your test since this behavior could be caused by earlier incomplete transactions or test setup issues, and should be further investigated. Regards, Rong Re: Agilex 7 R-Tile CXL Type-2 IP Hang with Incomplete CXL.cache Operations Hi, I think you can try these registers. Maybe check signal cxl_cache_mem_rx_frame in the intel_rtile_cxl_top_cxltyp2_ed/intel_rtile_cxl_ast_2331/. Regards, Rong Re: Fitter error in A5ED043AB23AI2V Example design A5ED065BB32AE4SR0 and A5ED043AB23AI2V are two different packages. Pls get the pin file of A5ED043A and arrange your PCIe and USB pins based on this. https://www.altera.com/design/devices/resources/pinouts Regards, Rong Re: Fitter error in A5ED043AB23AI2V Example design Pls share you pin assignments for check. Regards, Rong Re: Agilex 5E - PCIE PERST# pin - failing compilation Your pin_perst_n should be connected to PIN_BE25, pin_perst_n_1 to PIN_BM28. Regards, Rong Re: Cyclone V PCIe Reconfigure Busy Signal Hi, For those reconfig pins on the PCIe IP, you can wire all input signals(except clk and rst) to 0 if you don't need them. Connect clk to a slow clock and deassert rst. Regards, Rong Re: Fitter error in A5ED043AB23AI2V Example design Hi, Are you putting PCIe and USB3.1 on the same bank? using one XCVR? Do they share the same clock source? Regards, Rong Re: Agilex 5E - PCIE PERST# pin - failing compilation Hi, The error message points to your pcie_perst_n. Please make sure you don't use this pin for other purpose in your design. Then confirm the pin location and voltage in your qsf. Below are the settings from Agilex5 Modular Dev Kit FYR. set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to p0_pin_perst_n_i_reset_n set_instance_assignment -name WEAK_PULL_DOWN ON -to p0_pin_perst_n_i_reset_n Regards, Rong