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RongY_altera
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Re: Agilex7 M PCIe MCDMA: debug toolkit attachment
Hi Ju-Ti, You need to get Quartus work first. Otherwise, the generated example might be incomplete. The M-series dev kit has 2x MCIO from R-Tile, and 1x FMC from F-Tile. The Q25.3.1 Pro I'm using can generate MCDMA example design for the R-Tile on the Agilex7 I-series dev kit. For a simple test, you can choose "PIO using MCDMA Bypass" design. After a successful compilation, you can start to migrate the design to the M-series dev kit. If you want a jtag master to control the p0_hip_reconfig, you can connect them in the qsys, and comment/remove virtual pins in the qsf. The MCDMA supports several user modes. Some signals may not be enabled in the selected mode. Regards, Rong17Views0likes1CommentRe: Agilex 7 R-Tile PCIe Gen5: Avalon-ST DMA MWr TLP accepted by HIP but never received by Root Port
Hi Reza, If the RP is a CPU-based server, you'll needs to allocate a mem space for FPGA to write to. The mem space has a physical address and OS manages virtual address. Your MWr writes to the physical address. When doing a print at the server side, you'll see virtual address is used. Regards, Rong34Views0likes0CommentsRe: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer
The F-Tile is RP so it's type1. The CfgWr0 to EP BAR0 with FFFF_FFFFh is for finding the BAR0 size, right? Once the EP BAR0 is enabled, the RP can read/write to that BAR. Thus you need to set BDF on RP(type1), and enable BAR0 on EP(type0). Regards, Rong31Views0likes6CommentsRe: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer
I think something is mixed here. Most actions should be done to the type1 config register. But the mem space enable should be written to type0 command. Read @82h to get Link Rate and Link width Write 00h at @18h Read @18h to check previous Write Write 01h at @19h Read @19h to check previous Write Write 01h at @1Ah Read @1Ah to check previous Write Write 00h at @1Bh Read @1Bh to check previous Write Write 06h at @04h <------------------------to type0 command Read @04h to check previous Write Regards, Rong10Views0likes1CommentRe: quartus pro 25.3 bug?
I checked the PIO design and these two clocks you mentioned are from different sources, unlike what I've experienced in other designs. You can use a known user clock, normally 50MHz or 100MHz, to sample these two clocks, and monitor them with Transitional Type in a stp to record the changes. To check if they really lose sync, when the situation happens, and how frequent it happens. Also pls make sure the OSC clock is set in your project. Regards, Rong2Views0likes0Comments