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Re: F-Tile xcvr placement on DK-DEV-AGF023FA
Pasting full qsf will cause error. Here are the pins. set_location_assignment PIN_CK18 -to i_reconfig_clk set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to i_reconfig_clk set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to i_reconfig_clk set_location_assignment PIN_AD48 -to i_refclk2pll set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to i_refclk2pll set_location_assignment PIN_R49 -to o_tx_serial[0] set_location_assignment PIN_V52 -to o_tx_serial[1] set_location_assignment PIN_W49 -to o_tx_serial[2] set_location_assignment PIN_AB52 -to o_tx_serial[3] set_location_assignment PIN_AF52 -to o_tx_serial[4] set_location_assignment PIN_AK52 -to o_tx_serial[5] set_location_assignment PIN_AP52 -to o_tx_serial[6] set_location_assignment PIN_AV52 -to o_tx_serial[7] set_location_assignment PIN_K52 -to i_rx_serial[0] set_location_assignment PIN_P52 -to i_rx_serial[1] set_location_assignment PIN_R55 -to i_rx_serial[2] set_location_assignment PIN_W55 -to i_rx_serial[3] set_location_assignment PIN_AC55 -to i_rx_serial[4] set_location_assignment PIN_AG55 -to i_rx_serial[5] set_location_assignment PIN_AL55 -to i_rx_serial[6] set_location_assignment PIN_AR55 -to i_rx_serial[7] set_location_assignment PIN_T48 -to o_tx_serial_n[0] set_location_assignment PIN_U51 -to o_tx_serial_n[1] set_location_assignment PIN_Y48 -to o_tx_serial_n[2] set_location_assignment PIN_AA51 -to o_tx_serial_n[3] set_location_assignment PIN_AE51 -to o_tx_serial_n[4] set_location_assignment PIN_AJ51 -to o_tx_serial_n[5] set_location_assignment PIN_AN51 -to o_tx_serial_n[6] set_location_assignment PIN_AU51 -to o_tx_serial_n[7] set_location_assignment PIN_J51 -to i_rx_serial_n[0] set_location_assignment PIN_N51 -to i_rx_serial_n[1] set_location_assignment PIN_T54 -to i_rx_serial_n[2] set_location_assignment PIN_Y54 -to i_rx_serial_n[3] set_location_assignment PIN_AD54 -to i_rx_serial_n[4] set_location_assignment PIN_AH54 -to i_rx_serial_n[5] set_location_assignment PIN_AM54 -to i_rx_serial_n[6] set_location_assignment PIN_AT54 -to i_rx_serial_n[7] set_global_assignment -name DEVICE AGFD023R24C2E1VC #set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON1View0likes0CommentsRe: F-Tile xcvr placement on DK-DEV-AGF023FA
Using Q24.3.1 Pro to generate a FGT 400Gx8 example design and do migration to your target Dev Kit. The project can pass compilation. I suggest you create the example design based on the current Quartus version you're using, rather than upgrading a project created by another version. Regards, Rong2Views0likes0CommentsRe: F-Tile xcvr placement on DK-DEV-AGF023FA
You're right. The generated example design is not directly for your target dev kit thus your problem is likely something wrong when you do the design migration. For the DK-DEV-AGF023FA, your design should use Bank12C, FGTL12C_RX/TX_Q2/Q3 for the 400G, REFCLK_FGTL12C_Q3_RX_CH6P/N for the clock. Based on these pins, your 400G example design still has compilation error. Is my understanding correct? Regards, Rong7Views0likes0CommentsRe: CXL 2.0 support on the NEW Agilex™ 7 FPGA I-Series Development Kit (2x R-Tile and 1x F-Tile)
Hi, You can find your local/regional distributor at this link and contact them for further assistance. https://www.altera.com/contact Bothe Agilex7 I-series and M-series Dev Kits have R-Tile PCIe which supports CXL 2.0. Quartus 25.3.1 Pro can generated example designs for these two Dev Kits. Regards, Rong31Views0likes1CommentRe: F-Tile xcvr placement on DK-DEV-AGF023FA
Error(13076): The pin "ftile_eth|u0|eth_f_0|sip_inst|rd_ptr_sync|ml[0].lrm.CLK0[0]" has multiple drivers. >>You need to check this clock. The report says it is driven by multiple sources. >>You can also generate a 400G example design as a reference to confirm your clock connections. Regards, Rong17Views0likes2CommentsRe: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
I was not aware of this is a RP use case so my previous suggestions were not aligned to your needs. I noticed you have another similar topic in the forum with better statement. https://community.altera.com/discussions/fpga-device/avalon-mm-cyclone-v-hard-ip-for-pci-express-intel-fpga-ip---hard-reset-to-soft-r/350590 To prevent duplicate threads on the same issue, this topic will be closed. Thanks for your understanding. Regards, Rong18Views0likes0CommentsRe: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
"Once confirming PCIe link info correctly in lspci, you can try rescan and reset commands by referencing https://unix.stackexchange.com/questions/73908/how-to-reset-cycle-power-to-a-pcie-device" >>These are Linux commands to test your PCIe. No need to load driver. Regards, Rong28Views0likes2CommentsRe: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
Normally you need to follow the PCIe user guide to set hip_hard_reset_hwtcl to 0. I think you have done that and you're able to boot into Linux. Once confirming PCIe link info correctly in lspci, you can try rescan and reset commands by referencing https://unix.stackexchange.com/questions/73908/how-to-reset-cycle-power-to-a-pcie-device Regards, Rong22Views0likes4Comments