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xiaohao's avatar
xiaohao
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17 days ago

agilex 7 Platform Designer PIO addr width

I am using the PIO example design of the P-Tile AVST PCIe IP on Intel Agilex 7. The original design maps a 16KB RAM to BAR0. Since my design requires a larger address space, I modified the PCIe IP's ...
Pcie
RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
15 days ago

After you expand the BAR0 size, you'll need to expand some related modules inside PCIe PIO as well if you really need 2M size. if you'd like to check, a performance design like DMA doesn't always require a large BAR0. The way to use on-chip ram is important.

 

Since the PIO module does the AVST to AVMM transformation, here are some places I think you can try. Below filenames could be different from yours.

 

After the completion of Synthesis, you can find below module in ip/pcie_ed/pcie_ed_pio0/synth/pcie_ed_pio.v.

You may increase the PIPELINE_EN to a larger number.

 

This file ip/pcie_ed/intel_pcie_pio_g4_2431/synth/intel_pcie_bam_sch_intf_pipeline.sv does HIP to AVMM conversion. 

 

Right there, you can find a 16KB FIFO here. I think you need to expand both read and write FIFOs for a larger amount of data.

 

 

Regards,

Rong