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suleman's avatar
suleman
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1 year ago

JESD204B Latency Issue – Sample Shift Observed

Hi All, We are using a JESD204B IP core (Subclass 1) to receive trigger-synchronized data from an ADC. After every power cycle or reconfiguration, the lane alignment results in different latency. A...
Jesd
RongY_altera's avatar
RongY_altera
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1 year ago

Hi,

May I know which FPGA(and T-tile) and Quartus version?


Thanks,

Rong



suleman's avatar
suleman
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1 year ago

Hi @RongYuan ,

My apologies for late response.

Following are the details you asked.

FPGA: Intel Arria-10 (10AX048H3F34E2LG)

T-Tile:

Lanes: RX Four Lane

RX_0:

Channel: IOIBUF_X0_Y37_N112

PIN: AC30

RX_1:

Channel: IOIBUF_X0_Y35_N112

PIN: AB32

RX_2:

Channel: IOIBUF_X0_Y34_N112

PIN: AA30

RX_3:

Channel: IOIBUF_X0_Y33_N112

PIN: Y32

I/O Bank: 1D

Quartus: Std vq18.1

Thanks