sulemanNew Contributor8 months agoJESD204B Latency Issue – Sample Shift Observed Hi All, We are using a JESD204B IP core (Subclass 1) to receive trigger-synchronized data from an ADC. After every power cycle or reconfiguration, the lane alignment results in different latency. A...Show More
RongY_alteraContributor8 months agoHi,May I know which FPGA(and T-tile) and Quartus version? Thanks,Rong
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