Why is there a failure in the design if we are doing design migration for Agilex™ 3/ Agilex™ 5 FPGA from the Quartus® Prime Pro Edition software version 25.1.1 to 25.3?
Description Due to new implementation of the input reference clock buffer protection, there are additional ports being added in the reset sequencer IP, and some of the ports are being renamed from the Quartus® Prime Pro Edition software version 25.1.1 to 25.3. User will need to update the RTL with the updated ports name, if they have GTS Reset Sequencer IP ports connected to their IPs. Resolution For a workaround, users will require to update the existing port name to the new ports that are available in the Reset Sequencer IP. The existing ports that will require update will be: i_refclk_bus_out (in 25.1.1) --> i_src_rs_refclk_status_bus_out (in 25.3) o_shoreline_refclk_fail_stat (in 25.1.1) --> o_refclk_fail_status (in 25.3)How can I support legacy SFP modules with Agilex™ 5 FPGA and Agilex™ 3 FPGA GTS receivers?
Description Altera® Agilex™ 5 FPGA and Agilex™ 3 FPGA device GTS receivers cannot tolerate 2V pk-pk signals from legacy SFP modules. Resolution You can support legacy SFP modules by adding inline 6dB RF attenuators in between the SFP module and the Agilex™ 5 FPGA and Agilex™ 3 FPGA device GTS receiver. You must also power sequence the SFP module, ensuring that it powers up after the FPGA is configured. The Agilex™ 5 FPGA and Agilex™ 3 FPGA device GTS equalizer in Auto Adaptation mode should open the RX eye for reduced amplitude SFP+ signals. Altera recommend that you perform signal integrity analysis of your interface.Why are GTS transceiver tests including PCIe* enumeration failing on the Agilex™ 5 FPGA E-Series 065B Modular Development Kit (MK-A5E065BB32AES1)?
Description Due to a change in the Agilex™ 5 FPGA E-Series 065B Modular Development Kit (MK-A5E065BB32AES1) manufacturing test process, some boards have a corrupted FPGA image stored in the FPGA QSPI flash. This corrupt image results in failures in transceiver operation even if a new image is loaded via JTAG. Examples of issues include failure of the PCIe* to enumerate and SFP transceiver loopback tests failing. Resolution To fix this problem, follow these steps Ensure that the MAX® 10 FPGA POF image is updated as described in this KDB: Why does the GTS AXI Streaming IP for PCI Express* design example for Agilex™ 5 FPGAs fail to operate and enumerate in hardware when loaded from QSPI on the Agilex™ 5 FPGA E-Series 065B Modular Development Kit (MK-A5E065BB32AES1)? Download ghrd_a5ed065bb32ae6sr0_hps.jic to a host computer with the Quartus® Prime Pro Edition Programmer v25.3 or newer to update the Agilex™ 5 FPGA E-Series 065B Modular Development Kit FPGA QSPI flash. Set the Agilex™ 5 FPGA Modular Development Kit carrier board switch S13-3 and S13-4 to "OFF" so the USB JTAG option is selected and the Agilex™ 5 FPGA is on the JTAG chain. See switch setting in this photo: Connect the micro USB cable to the Agilex™ 5 FPGA Modular Development kit front panel JTAG connector (J35) and attach other end to host computer. Bring up the Quartus® Prime Pro Edition (25.3 or newer) Programmer GUI, select "Auto Detect" . Your display should be similar to the one shown below: Select the A5EC065BB32 device, right click and change file to ghrd_a5ed065bb32ae6sr0_hps.jic. Select "Program/Configure" and "Verify" for the MT25QU02G device as shown below: Click "Start" to begin the programming process. The programming process takes approximately 5 minutes to complete. Power cycle the board for the new image to be loaded. This manufacturing problem is resolved in production versions of the Agilex™ 5 FPGA Modular Development Kit.Why am I seeing some packet drop/loss when using the F-tile Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled 100G designs?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, 25.3 and 25.3.1, you may see traffic failures with packet drop/loss when using the F-tile Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled 100G designs. Resolution Add the solution or the workaround to fix the problem or bug. Additional Information Currently there is no workaround for this problem. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Training (AN/LT) IP with ECC enabled designs?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1, you may see linkup problem for multi-port GTS Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) IP designs when ECC is enabled. Resolution Currently there is no workaround for this problem. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why am I seeing linkup problem for the GTS Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) multirate IP for HVIO PLL enabled 25G rate designs?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1, you may see linkup problem for the GTS Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) multirate designs. This problem may happen when using 25G multirate designs with HVIO PLL option enabled. Resolution Currently there is no workaround for this problem. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why does the Multi-Channel DMA FPGA IP for PCI Express* stall or stop operating when the Q_SIZE parameter is configured to 0x10?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.2 and later, the Multi-Channel DMA FPGA IP for PCI Express* may stall or cease operation when the Q_SIZE parameter is set to 0x10. Resolution The recommended workaround is to limit Q_SIZE to 0xF. If your design requires a Q_SIZE of 0x10, upgrade to the Quartus® Prime Pro Edition software version 25.3.1, regenerate the Multi-Channel DMA FPGA IP for PCI Express, and recompile the design to ensure the fix takes effect.Why does the GTS SDI II IP Multi-rate Serial Loopback Design Example fail to achieve lock on Agilex™ 5 FPGA E-Series Premium Development Kit at 12G data rate?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1, you may observe the rx_align, rx_frame and rx_trs signals fail to achieve lock when running the GTS SDI II IP Multi-rate Serial Loopback Design Example on Agilex™ 5 FPGA E-Series Premium Development Kit at 12G data rate. Resolution There is no workaround. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.How can I support legacy SFP modules with Agilex™ 7 FPGA F-Tile receivers?
Description Altera® Agilex™ 7 FPGA device F-Tile receivers cannot tolerate 2V pk-pk signals from legacy SFP modules. Resolution You can support legacy SFP modules by adding inline 6dB RF attenuators in between the SFP module and the Agilex™ 7 device F-Tile receiver. You must also power sequence the SFP module, ensuring that it powers up after the FPGA is configured. The Agilex™ 7 device F-Tile equalizer in Auto Adaptation mode should open the RX eye for reduced amplitude SFP+ signals.Why does HPS Coresight Trace Clock detection fail with Quartus® Prime Pro version 25.3?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, the 'tpiu_trace_ctl' port is now tied to 0, causing a failure that did not occur when the port was left unconnected in previous versions. Resolution To work around this problem, perform the following steps: Run the IP Generation stage of the Quartus® compilation flow. Modify the generated file from IP Generation: Change in file: <ip_path>/hps_subsys/agilex_hps/intel_sundancemesa_hps_100/synth/agilex_hps_intel_sundancemesa_hps_100_*.v Original: Modified: 3. Continue the Quartus® Compilation flow from Analysis & Synthesis onward. (Note: Do not run the IP Generation stage again) This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.
