Why do I see the HPS on Intel Agilex® SoC devices fail to boot, or observe some unexpected functional failures at run time?
Description Due to a problem in the device manager firmware, you might fail to read/write certain RAMs on some Intel Agilex® SoC devices. Impacted HPS RAMs include L2 cache, OCRAM, CCU, USB, CoreSight, and EMAC. You might observe the following HPS boot failures: HPS hangs at dcache memory write and read after executing the dcache_enable function in FSBL UART printout stops after “DDR: 8192 MiB” UART printout stops after “Loading Environment from MMC… ***” UART printout stops after “Verifying Hash Integrity … crc32” Various unexpected functional failures depending on the faulty RAM location Resolution To resolve this problem, update to the latest device manager firmware for the Intel® Quartus® Prime Pro Edition Software v21.2, 21.3, 21.4, 22.1, and 22.2. The latest device manager firmware is available from the following link: What is the latest device firmware for Intel Agilex® and Intel® Stratix® 10 devices? This problem is fixed beginning with version 22.4 of the Intel® Quartus® Prime Pro Edition software.Have the Arria® 10 PCI Express* Testbench required simulation files changed in version 24.2 of the Quartus® Prime Design Software?
Description Yes, as part of the ongoing improvements and streamlining of the Quartus® Prime Design Software core device family models (altera_mf etc.) the PCI Express* link-partner root-port BFMs that shipped as part of the altera_pcie_a10_tbed (IP version 19.1) were updated starting in version 24.2 to use Arria® 10 FPGA based primitives rather than the previously used Stratix® II FPGA primitives without a corresponding IP version increase. Attempting to use device libraries compiled from newer versions of Quartus® Prime Design Software with a testbench generated from an older version of the Quartus® Prime Pro software may lead to runtime errors from simulators about invalid module parameters of the form: Error! Unknown INTENDED_DEVICE_FAMILY=Stratix II. Resolution To resolve this problem, it is recommended to always re-generate Altera IP with the same version of the Quartus® Prime Pro software being used.Error: niosv_g_dcache.sv: part-select direction is opposite from prefix index direction
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 24.3.1, 25.1, and Quartus® Prime Standard Edition Software version 24.1 When the Nios® V/g processor is configured with No Data Cache and enabled with Error Detection and ECC Status Reporting, performing Analysis and Synthesis fails with the error "niosv_g_dcache.sv: part-select direction is opposite from prefix index direction". Note that this issue has no relationship with No Instruction Cache. Figure. Nios® V/g Processor Setting to Replicate the Error Resolution To work around this error, Select 1Kbytes Data Cache. Apply a Peripheral Region that covers the whole Nios® V processor’s data_manager address map Enable Error Detection and ECC Status Reporting. By implementing Peripheral Region, the above settings can emulate an ECC-enabled Nios® V processor system that operates without caches. Figure. Workaround (in this example, the whole Nios® V processor’s data_manager address map is 1GB) This problem is scheduled to be fixed in a future release of the Quartus® Prime Edition Software.Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows and Linux below This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why isn’t a programming (SOF) file generated for the F-Tile Dynamic Reconfiguration Suite IP available for Example Designs when using the Quartus® Prime Pro Edition software versions 25.3 and earlier?
Description Due to starting from the Quartus® Prime Pro Edition software version 25.3 and earlier, it is compulsory to connect all the I/O ports to the correct PIN location. If any of the design I/O ports are floating and not properly connected, Quartus software will not be able to generate the programming file for the design compiled. This is mentioned in the Quartus Prime Pro Edition User Guide version 25.1.1 in 1.2. Generating Secondary Programming Files and provide the guidelines to the user on how to fix the Quartus software critical warning and successfully create the programming file for your design. Why don’t I get a programming file when I compile with the.... Similar programming (SOF) file generation problem you may observe when you generate the F-Tile Dynamic Reconfiguration Suite IP Example Designs by selecting Target Development Kit with option 1) Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (Production 1 4xF-Tile) DK-SI-AGI027FA or 2) Agilex 7™ FPGA I-Series Transceiver-SoC Development Kit (Production 2 4xF-Tile) DK-SI-AGI027FC. As shown in the figure below. Resolution As a workaround, generate the F-Tile Dynamic Reconfiguration Suite IP Example Designs by selecting the Target Development Kit with the option you want and compiling the design. Review the I/O Assignment Warnings report, found in the Place sub-section of the Fitter section of the compilation report. Alternatively, review the <revision>.fit.plan.rpt report file. For any pins in the I/O Assignment Warnings report that are reported as “Missing location assignment” or “Missing I/O standard,” add the appropriate location or I/O standard assignment. For help making these assignments, refer to Assigning I/O Pins. After adding any required assignments, recompile the design to generate a programming file. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why is the external loopback test failing for the GTS Dynamic Reconfiguration Controller IP in the GTS PMA/FEC Direct PHY example design?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1 and 25.3, you may notice that the external loopback test is not working correctly for the GTS Dynamic Reconfiguration Controller IP for the GTS PMA/FEC Direct PHY example design. This is due to incorrect settings in the hardware tcl scripts inside the “hwtest” folder. You may notice the external loopback test shows “DR Test Passed” in the system console; however, it does not change the DR profile for GTS PMA/FEC Direct PHY IP. Resolution As a workaround, modify the tcl script file as shown below: Go to “hardware_test_design/hwtest” folder: Replace the “dr_ctrl_csr_reg_map.tcl ” file inside the “hwtest/src” folder with the attached file. Replace the “dr_dphy_test.tcl” file inside the “hwtest/tests” folder with the attached file (hwtest.zip). This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why doesn’t the output frequency of the System PLL match the setting in the GTS System PLL Clocks IP?
Description Due to a device problem, some reference clock frequency options in the dropdown list in the IP are no longer valid for certain output frequencies. Selecting the invalid reference clock options will result in incorrect System PLL output frequencies. However, the System PLL lock status signal remains asserted. Resolution Download the TCL script (find_mcnt.tcl) to determine whether the reference clock frequency selected in the GTS System PLL Clocks IP is valid. If the reference clock frequency is not valid, the script recommends the following workarounds: List of alternate reference clock frequencies while keeping the same output frequency. Two alternate higher System PLL output frequencies while keeping the same reference clock frequency. You need to run the transceiver channels driven by the impacted System PLLs in custom cadence mode. In certain cases, the script will suggest that the same output & input clock frequencies can be retained. This option is possible only if you install the patch for the Quartus® Prime Pro Edition Software version 25.3 or migrate to future Quartus Prime Pro Edition Software versions. Copy the TCL script (find_mcnt.tcl) to each of the generated IP folders of the GTS System PLL Clocks IP in your Quartus Prime Pro Edition Software project. For the Linux* operating system, change directory to the IP folder and execute the command "tclsh find_mcnt.tcl". For Windows* operating system, run the script from the Tcl Console within the Quartus Prime Pro Edition Software GUI. A patch is available to fix this problem for the Quartus Prime Pro Edition software version 25.3. Download and install Patch 0.15 from the files below. Recommended actions: Customer Design Status Recommended Actions Design not impacted If the design is final and there is no plan to change the System PLL output frequency or reference clock frequency in future revisions, no further action is needed. If you change the design in the future, either migrate your design to Quartus Prime Pro Edition Software versions 25.3.1 or later, or install the patch for Quartus Prime Pro Edition Software version 25.3. Design impacted Implement one of the workarounds suggested. In addition, migrate your design to the Quartus Prime Pro Edition Software version 25.3.1 or later. If you need to keep your design in the Quartus Prime Pro Edition Software version 25.3, install the patch, re-generate the GTS System PLL Clocks IP, and recompile your Quartus project. The invalid reference clock frequency options will be removed in a future Quartus Prime Pro Edition Software version.What problems must I know about in the Quartus® Prime Pro Edition Software version 21.2?
Description If you are using the Quartus® Prime Pro Edition Software version 21.2, consider the following important solutions: Resolution Why is the Configuration via Protocol (CvP) Initialization / CvP Update not functioning in Agilex™ 7 F-Tile & R-Tile devices? Why do I see functional errors in hardware when using the Stratix® 10 10GBASE-KR PHY IP core? Why does my Altera® Phylite IP fail in hardware when the VCO is running around 1066 MHz (with Interface frequency around 266/533/1066MHz)? Why does my Agilex™ 7 FPGA tri-state GPIO pin fail in hardware?Why is the o_rx_pfc port enabled for longer durations than normal when generating designs at 400G SIP using the F-Tile Ethernet Hard IP with Priority Flow Control (PFC) enabled?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may see longer durations of “o_rx_pfc” port enabled in the example designs generated using the F-Tile Ethernet Hard IP at data rates of 400G SIP with PFC enabled. When PFC is enabled, if packets received are more than the maximum configured frame size of the receiver, along with which if packet truncation is also enabled on the receiver side, then the packets are truncated, causing data_valid to deassert. This deasserted data_valid signal is affecting the counters of o_rx_pfc to stretch the pause signal duration. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why does the F-Tile Triple-Speed Ethernet IP Design Example fail during simulation on Windows using ModelSim* in the Quartus® Prime Pro Edition Software version 24.3?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3, the F-Tile Triple-Speed Ethernet (TSE) IP Design Example variant - “10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2xTBI PCS with F-Tile FGT Transceiver” - may fail during simulation on Windows platforms using ModelSim*. This problem occurs because the simulation script generated for the design example contains incorrect backslash (“\”) usage, which is not compatible with Windows* path formatting requirements. Resolution There is no workaround to this problem in the Quartus® Prime Pro Edition Software version 24.3. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.
