Why does the DisplayPort example design fail to generate in Quartus® Prime Pro Edition Software version 26.1?
Description Due to a problem in Quartus® Prime Pro Edition Software version 26.1, you may see a software build failure when generating the DisplayPort FPGA IP Design Example. In this condition, the generated Nios® V software build fails in debug.c because the load_resolutions() call passes modes_found instead of &modes_found. You may see an error similar to the following: debug.c:486:94: error: passing argument 4 of 'load_resolutions' makes pointer from integer without a cast note: expected 'int *' but argument is of type 'int' Error: Failed to generate example design Resolution To work around this problem, modify debug.c line 486 either in the installed source or in the generated example design, and then regenerate or rebuild the design. Change: load_resolutions (1, mode_param_array, &dsc_data_pps_parameters, modes_found); to: load_resolutions (1, mode_param_array, &dsc_data_pps_parameters, &modes_found); This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.Why does the R-tile AXI Multichannel DMA IP for PCI Express* Example Design (AXI-S Packet Generate/Check variant) generation fail with Enable User MSI-X IP is selected?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 25.3, 25.3.1 and 26.1, Example Design generation fails for the R-Tile AXI Multichannel DMA IP for PCI Express* when: AXI-S Packet Generate/Check mode is selected Enable User MSI-X option is selected under the PCIe Settings --> MCDMA Settings tab The problem is observed a few minutes after clicking the Generate Example Design button. Quartus® Prime Pro Edition Software reports an error in the Generate Example Design Completed window and the Example Design is not generated successfully. An example of the message observed in the Generate Example Design Completed window is shown below: Error: add_connection GEN_CHK_M0.usr_msix DUT.user_msix: Cannot connect GEN_CHK_M0.usr_msix to DUT.user_msix. Error: Failed to generate example design example_design to: <path> This problem applies only to the AXI-S Packet Generator/Checker variant of the Example Design. The AXI Multichannel DMA IP itself can still be generated successfully when the Enable User MSI-X option is selected. Resolution To work around this problem, do not select the Enable User MSI-X option when generating the R-Tile AXI Multichannel DMA IP for PCI Express* Example Design. There is no other workaround for Quartus Prime Pro Edition Software versions 25.3, 25.3.1, and 26.1. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.Why does simulation of the F-Tile Multi Channel DMA FPGA IP for PCI Express* Design Example (Packet Generate/Check variant) fail when using Siemens Questa* simulator in Quartus® Prime Pro Edition Software versions 25.3.1 and 26.1?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 25.3.1 and 26.1, simulation of the F-Tile Multi Channel DMA FPGA IP for PCI Express* Design Example with the Packet Generate/Check variant may fail when using the Siemens Questa* simulator. The failure is observed after the DMA queue reset sequence finishes, and a PIO register write is issued. Simulation then stalls with no further activity and terminates with an inactivity timeout after some time. An example of the messages observed in the simulation log is shown below: INFO: 43000 ns H2D: Got Status for Channel 0 INFO: 43000 ns D2H: Performing Channel 0 Queue Reset INFO: 47000 ns D2H: Channel 0 Queue Reset...done INFO: 47000 ns PIO_WRITE_REG 8000000100001000 FATAL: 4000000 ns Simulation stopped due to inactivity! FAILURE: Simulation stopped due to Fatal error! FAILURE: Simulation stopped due to error! ** Note: $stop : ../../../ip/pcie_ed_sim_tb/dut_pcie_tb_ip/intel_pcie_ftile_tbed_100/sim/altpcietb_g3bfm_log.v(146) Time: 4 ms Iteration: 3 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/g_bfm/p_dut_ep/altpcietb_bfm_top_rp/g_bfm/u1/rp/inst/apps/genblk1/drvr Break at ../../../ip/pcie_ed_sim_tb/dut_pcie_tb_ip/intel_pcie_ftile_tbed_100/sim/altpcietb_g3bfm_log.v line 146 This issue affects simulation only and does not impact hardware functionality. Resolution To work around this problem, generate the F-Tile Multi Channel DMA FPGA IP for PCI Express Design Example (Packet Generate/Check variant) and run simulation using Quartus® Prime Pro Edition Software version 25.1.1. The problem is not observed in that release. There is no other workaround for Quartus® Prime Pro Edition Software versions 25.3.1 and 26.1. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does the R-Tile AXI Multichannel DMA IP for PCI Express* AXI-S Packet Generate/Check Example Design generation fail with Enable User FLR is selected?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 25.3 and later, Example Design generation fails for the R-Tile AXI Multichannel DMA IP for PCI Express* when: AXI-S Packet Generate/Check mode is selected Enable User FLR option is selected under the PCIe Settings --> MCDMA Settings tab. The problem is observed a few minutes after clicking the Generate Example Design button. Quartus® Prime Pro Edition Software reports an error in the Generate Example Design Completed window and the Example Design is not generated successfully. An example of the message observed in the Generate Example Design Completed window is shown below: Error: pcie_axi_mcdma_0: Fail .qsys synthesis generation Error: pcie_axi_mcdma_0: Unable to generated HDL Files for the system .qsys Error: Failed to generate example design example_design to: <path> Generate Example Design: completed with errors. This problem applies only to the AXI-S Packet Generator/Checker variant of the Example Design. The AXI Multichannel DMA IP itself can still be generated successfully when the Enable User FLR option is selected. Resolution To work around this problem, do not select the Enable User FLR option when generating the R-Tile AXI Multichannel DMA IP for PCI Express* AXI-S Packet Generate/Check Example Design. There is currently no other workaround for Quartus® Prime Pro Edition Software versions 25.3 and later. This problem is planned to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why is the Avalon MM interface optimized away when using the SDI Audio Embed or SDI Audio Extract IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, the SDI Audio Embed IP and SDI Audio Extract IP might show incorrect behaviour when the generated IP name is audio_embed or audio_extract. In this condition, the affected output ports are left undriven and connected to the default value gnd, you will see messages similar to those shown below: Output port "reg_waitrequest" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_waitrequest" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Resolution To work around this problem, use a different IP name to avoid a naming that conflicts with the generated HDL module naming used by the Quartus® Prime Pro Software for the SDI Audio Embed or SDI Audio Extract IP. For example: Do not name the SDI Audio Embed IP as audio_embed. Do not name the SDI Audio Extract IP as audio_extract. Regenerate the IP after renaming it to a non-conflicting name. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.Why does Agilex® 7 FPGA M-Series fail to launch U-Boot proper after a Warm reset in release 25.3.1 and later?
Description Due to corruption in the device tree on the Warm reset flow in the Agilex® 7 FPGA M-Series device, the resolution of the u-boot,spl-boot-order = &mmc node fails at the re-entry of the U-Boot SPL, resulting in the loading of the U-Boot proper failing. The error observed is the following: Hit any key to stop autoboot: 0 SOCFPGA_AGILEX7M # reset -w resetting ... Do warm reset now... U-Boot SPL 2025.10 (Dec 11 2025 - 10:49:42 +0000) Reset state: Warm (Triggered by MPU 0) MPU 1350000 kHz L4 Main 400000 kHz L4 sys free 100000 kHz L4 MP 200000 kHz L4 SP 100000 kHz SDMMC 50000 kHz HBM: SDRAM init in progress ... HBM: Calibration success HBM: Warning: DRAM size from device tree (2048 MiB) mismatch with hardware (4096 MiB). HBM: 2048 MiB HBM: size check success HBM: firewall init success HBM init success board_boot_order: no valid element spl-boot-order list SPL: failed to boot from all boot devices ERROR ### Please RESET the board This problem is observed regardless of the method used to apply the Warm reset, and this is present in release 25.3.1 and later. Resolution There is no workaround for this problem. This will be fixed in a future release.Why does the simulation of my Altera® AXI BFMs fail?
Description In the Quartus® Prime Pro Edition Software, a VHDL testbench generated by Visual Designer Studio or Platform Designer using Altera® AXI BFM will error out. The Altera AXI BFMs only support testbenches generated in Verilog HDL or System Verilog HDL. In the Siemens* Questa* Simulator, the error message may be similar to this: ** Error: <file name>.vhd: (vcom-1598) Library "<library name>" not found. Resolution To avoid this problem, generate the testbench in Verilog HDL or System Verilog HDL.Why is Agilex® 5 FPGA HPS IP's Auto-Place IP failed to place the selected peripheral after Apply Selections ?
Description When assigning peripherals to the HPS IO, you may encounter a placement limitation due to the peripheral cannot fit into the available unused IO locations. The error message is not displayed in the Parameterization Messages but appears in the Messages window after running Auto-Place IP. This snapshot is an example: Resolution This problem is plan to be fix in Quartus® Prime Pro Edition Software v26.1.Why does the F-Tile System PLL fail to lock when the reference clock is active only after configuration?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you might observe the F-Tile System PLL lock failure when your design has both below requirements: More than one System PLL are enabled in one F-Tile, e.g. syspll0 and syspll1 One System PLL reference clock source will only be active after the other System PLL is locked. E.g. syspll0 refclk is active only after syspll1 is locked. Failure Symptom: The later System PLL will never lock. E.g syspll0 refclk is active only after syspll1 is locked, then syspll0 could never lock. Background: When a System PLL reference clock source is not active at configuration, then all System PLL reference clock must unselect parameter And the F-Tile Reference and System PLL Clocks FPGA IP will expose below control signals for each System PLL: refclock_ready[n] en_refclk_fgt_i Expected behavior: For each System PLL #n, after its reference clock source #i is active, then we can drive refclock_ready[n] and en_refclk_fgt_i to get System PLL #n locked independently from other System PLL. Root Cause: A SSM (Secure Socket Manager) FW bug causes the control signals of the 3 System PLLs can not work independently. Resolution There is no workaround available. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why Can't I Program Using Active Serial Programming with my USB Blaster III?
Description Due to a firmware issue the USB Blaster III Development cable may not have the correct product ID and may inadvertently disabled the active serial programming feature. Resolution To resolve this issue the Product ID of the cable should be updated to (6023). Perform the following steps on Windows to update the ID. Download and Install the FT_PROG.exe the EEPROM Programming Utility from FTDI https://ftdichip.com/utilities/ Plug-in your USB Blaster III development cable into your computer. Uninstall the USB Blaster III device driver from the device manager. Open the Windows Device Manager. Find the group called JTAG cables, under this group there should be a USB Blaster III device. Right Click on the USB Blaster III device and Click Uninstall. Tick "Attempt to delete the driver for this device" or "Delete the driver software for this device" during uninstallation. This prevents the UB3 driver from being automatically reinstalled. Install the FTDI Device driver. Open the Windows Device Manager. Find the group called Other Devices. In the group Other Devices there may be several USB Blaster III devices. To Identify the correct USB Blaster III device Right click on each USB Blaster III device and click Properties. Find USB Blaster III device that contains values that end with MI_00 Once Identified, Right click on correct USB Blaster III device and click Update driver To Update driver click Browse my computer for drivers Search and select the USB Blaster III driver directory under your Quartus installation. <Quartus Path>\qdrivers\quartus\drivers\usb-blaster-iii Click Let me pick from a list of available drivers on my computer. If, Select your device’s type from the list below, choose Universal Serial Bus controllers. When selecting a driver click the FTDI manufacturer then select USB Serial Converter A Version: 2.12.36.4 and click the Next button. Program your USB Blaster III Development Cable with FT_PROG.exe to update your product ID. Open the FT_PROG.exe from FTDI installed in step 1. From the DEVICES menu click Scan and Parse to bring up your USB Blaster III Device Under the Device Tree select the section called USB Device Descriptor This should contain a property called Product ID and should have a value of 6023, change this to 6023 if it is not set to this value. Once changed, under the DEVICES menu click Program to flash the EEPROM Uninstall the FTDI driver installed in step 4. Open the Windows Device Manager. Find the group Universal Serial Sub controllers In the Universal Serial Bus controllers right click on the USB Serial Converter A and Click Uninstall. Do not tick "Attempt to delete the driver for this device" or "Delete the driver software for this device". Re-Install the USB Blaster III device driver. Open the Windows Device Manager. Find the group called Other Devices. In the group Other Devices there may be several USB Serial Port devices or USB Blaster III devices. To Identify the correct USB Serial Port device Right click on each USB Serial Port device and click Properties. Find USB Serial Port device that contains values that end with MI_00 Once Identified, Right click on correct USB Blaster III device and click Update driver To Update driver click Browse my computer for drivers Search and select the USB Blaster III driver directory under your Quartus installation. <Quartus Path>\qdrivers\quartus\drivers\usb-blaster-iii Click the Next button. Windows should show USB Blaster III driver installed. Verify USB Blaster III device has the correct Product ID. Open the Windows Device Manager. Find the group called JTAG cables, under this group there should be a USB Blaster III device. Right click on each USB Blaster III device and click Properties. Values should contain PID_6023 in the string, if not unplug and re-plugin the device. Open Quartus Programmer and Validate that the Active Serial programing is now available.
