embedded applications layer
84 TopicsMailbox Client HAL API: Erroneous behavior in flash erase boundary checks (Agilex 3 / Nios V)
Hi, I am currently working on an Agilex 3 platform using the Nios V in Quartus Prime Pro 25.3. I discovered unexpected behavior in the Mailbox Client HAL API when trying to erase 32K blocks of flash. In the file intel_mailbox_client_flash.c in function mailbox_client_flash_erase_block: The function receives a dynamic block_size as an argument but ignores it during the boundary check, relying instead on the global dev_info->region_info.block_size. Because it checks against the maximum hardware block_size (i.e., 64K) instead of the actual block_size parameter passed to the function, it mistakenly blocks legitimate erase commands at the final sectors of the region. Below is the code snippet: int mailbox_client_flash_erase_block(intel_mailbox_client* fd, int block_offset, int block_size) { if(block_offset < 0 || block_offset > dev_info->region_info.region_size - dev_info->region_info.block_size || (block_offset & (SZ_4K - 1)) != 0) { return -EINVAL; } } I suggest changing the boundary check to use the local block_size parameter that was explicitly passed to the function: if(block_offset < 0 || block_offset > dev_info->region_info.region_size - block_size || (block_offset & (SZ_4K - 1)) != 0) { return -EINVAL; } A similar logic flaw exists in the caller function mailbox_client_flash_erase. The input validation check uses the static hardware block size (dev_info->region_info.block_size) instead of taking the requested length into account. I suppose this check should prevent out-of-bounds erases in the first place, so checking if there is one 64K block left in the flash is actually pointless. int mailbox_client_flash_erase(intel_mailbox_client* fd, int offset, int length) { if(offset < 0 || offset > dev_info->region_info.region_size - dev_info->region_info.block_size) { return -EINVAL; } } I suggest using: if(offset < 0 || offset > dev_info->region_info.region_size - length) { return -EINVAL; } Any feedback on this behavior would be appreciated. Thanks!43Views1like2CommentsIntroducing the Altera Community AI Responder — Beta
Altera is introducing the AI Responder, an assistant built into the Altera Community to help provide faster, context-aware guidance for Altera product questions. It uses relevant public Altera documentation and Knowledge Database content, with coverage continuing to expand. The AI Responder may provide source references and can hand off complex or out-of-scope questions to an Altera subject-matter expert. As a beta feature, responses may contain errors or omissions, so please review the sources and verify technical guidance against official Altera documentation before implementation. If the response does not fully address your question, add more context and tag ai_responder to continue the discussion. We welcome your feedback as we improve the Community experience.21Views0likes0CommentsDual Port Nios V BSP error
I've created a Nios V qsys with dual port onchip memory in Quartus Pro 26.1 True dual port, first port connected to instruction manager, second - to data manager. Base addresses automatically assigned the same to both. But i'am unable to create the BSP due to memory regions overlapping error! Of course the addresses are same - its the same physical onchip memory! Any solytion, please? Regards, Vlad.282Views0likes9Commentsnot able to use multiple niosV cores at the same time
when I run ultiple niosV cores at the same time im not able to acess each of them even though i am able to detect them , i am faced with even though detecting gives me and i am unable to use the cores likewise this is my file on platform designer280Views1like7CommentsNIOS II "Verify failed" for on-chip memory 128k
Hello! I'm using a Cyclone 10LP FPGA 10CL055YU484I7G FPGA. I have a 11k size program for NIOS II. I have a large on chip RAM (because I have a larger program which I want to use later) of 128k. Everything compiles and links OK. But when I try to download the program I get a "Verify failed between address 0x20000 and 0x2FFFF". The 128K memory is located 0x20000 to 0x3FFFF If I reduce the RAM to 32K, for example, everything works great!!. The initialize memory content option is turned on for the memory The BOOT RAM starts at 0x00000 If I download a bigger program (117k), I still get the same error. Thanks267Views0likes3CommentsWhere is FreeRTOS-Plus-TCP Design
Hello, Can someone show or share me the link or design data regarding "FreeRTOS-Plus-TCP" mentioned in Nios V Processor SW Dev. HB? https://docs.altera.com/r/docs/743810/25.3.1/nios-v-processor-software-developer-handbook/enabling-freertos-plus-tc Thank you.Solved321Views0likes7CommentsNiosV and juart-terminal
I had a project which works fine under niosII. I upgrade all the project with niosv and all seems fine except printing values in juart-terminal. Here is the main code : #include <stdio.h> #include "system.h" #include "altera_avalon_pio_regs.h" #include <altera_avalon_i2c.h> #include <unistd.h> #include <string.h> int main() { //* ALT_AVALON_I2C_DEV_t *i2c_dev; //pointer to instance structure alt_u8 txbuffer[20]; alt_u8 rxbuffer[20]; float co2Concentration = 0; float temperature = 0; float humidity = 0; alt_u32 co2U32 = 0; alt_u32 tempU32 = 0; alt_u32 humU32 = 0; ALT_AVALON_I2C_STATUS_CODE status; i2c_dev = alt_avalon_i2c_open("/dev/i2c"); //Ouverture du périphérique i2c et récupération d'un pointeur if (NULL==i2c_dev) { printf("Error: Cannot find /dev/i2c\n"); return 1; } //set the address of the device using alt_avalon_i2c_master_target_set(i2c_dev,0x61); //Définition de l'adresse du composant adressé 0x61 pour le SCD30 txbuffer[0]=0x00; txbuffer[1]=0x10; txbuffer[2]=0x00; txbuffer[3]=0x00; txbuffer[4]=0x81; //Remplissage du buffer pour configurer le SDC30 en Continous measurement status=alt_avalon_i2c_master_tx(i2c_dev,txbuffer, 5,ALT_AVALON_I2C_NO_INTERRUPTS); //Envoi du buffer au composant if (status!=ALT_AVALON_I2C_SUCCESS) return 1; //FAIL while(1) { txbuffer[0]=0x02; txbuffer[1]=0x02; //Remplissage du buffer pour déterminer si les données sont prêtes alt_avalon_i2c_master_tx(i2c_dev,txbuffer, 2,ALT_AVALON_I2C_NO_INTERRUPTS); //Envoi du buffer au composant rxbuffer[1]=0x00; usleep(3000); // Il faut attendre au moins 3ms avant de demander la réponse alt_avalon_i2c_master_rx(i2c_dev,rxbuffer, 3,ALT_AVALON_I2C_NO_INTERRUPTS); //Récupération de la réponse du composant si rxbuffer[1]==0x01 alors les données sont prêtes if(rxbuffer[1]==0x01) { txbuffer[0]=0x03; txbuffer[1]=0x00; //Remplissage du buffer pour la lecture des données alt_avalon_i2c_master_tx(i2c_dev,txbuffer, 2, ALT_AVALON_I2C_NO_INTERRUPTS); //Envoi du buffer de lecture et récupération des données usleep(3000); //Wait 3ms before data available alt_avalon_i2c_master_rx(i2c_dev,rxbuffer, 18,ALT_AVALON_I2C_NO_INTERRUPTS); //Read datas co2U32 = (alt_u32)((((alt_u32)rxbuffer[0]) << 24) | (((alt_u32)rxbuffer[1]) << 16) | (((alt_u32)rxbuffer[3]) << 8) | ((alt_u32)rxbuffer[4])); tempU32 = (alt_u32)((((alt_u32)rxbuffer[6]) << 24) | (((alt_u32)rxbuffer[7]) << 16) | (((alt_u32)rxbuffer[9]) << 8) | ((alt_u32)rxbuffer[10])); humU32 = (alt_u32)((((alt_u32)rxbuffer[12]) << 24) | (((alt_u32)rxbuffer[13]) << 16) | (((alt_u32)rxbuffer[15]) << 8) | ((alt_u32)rxbuffer[16])); memcpy(&co2Concentration, &co2U32, sizeof(co2Concentration)); memcpy(&temperature, &tempU32, sizeof(temperature)); memcpy(&humidity, &humU32, sizeof(humidity)); } printf("---------------------------------------------------------\n"); printf("SCD30\n"); printf("Concentration de CO2 : %f ppm\n",co2Concentration); printf("Température : %.1f °C\n",temperature); printf("Humidité relative : %.1f %% \n",humidity); usleep(500000); } } I put a breakpoint just before the printf and the values are good : but when i print the values in the juart-terminal : I can't figure out why the printf does not work as i expect. Someone could help me to understand this problem ? Thanks EricSolved525Views0likes14CommentsNiosV µC/OS-II TCP-IP debug
Hello, I am trying design a NiosV program with TCP/IP based on this example design: Arria® 10 FPGA – Simple Socket Server for the Nios® V/m Processor Design Example I don't have the proposed devkit, so I compiled it for two different Arria10 targets. For both targets, I get the error: [network_init] Failed to NetIF_Start(): (2010). TSE link seems to be OK. Since I'm not experienced with Nios, I'm looking for help to debug it. Thanks591Views0likes15CommentsAshlingRISCFree IDE Build system: 'source directory does not appear to contain CMakeLists.txt"
Hello Altera Gurus, I am now having much trouble building my projects with the AshlingRISCFree IDE using a NIOSV/m processor on a MAX10 FPGA targeted at a MAX10 Development kit. I am using Quartus Standard edition 25.1 on a Windows 10 PC. The process i am following is this: I created an FPGA top level System Verilog file for a new MAX10 Project. created a Qsys Platform which has a NIOSV/m processor connected to a onchip RAM for program storage and a onchip RAM for the DMA data. Added one mSGDMA engine for transmit data operations Added a second mSGDMA engine for receivedata operations Added two RAM onchip memories for the DMA decsriptors and wired up everything created the address map and interrupt mapping saved and generated the Qsys platform In the top level SV file is loopback the Tx -> RX for the two mSGDMAs Used the niosv-bsp-editor in a niosv console to created a BSP using the Qsys sopcinfo file Generated the BSP, created a simple C main application to configure the mSGDMAs and NIOSV/ m processor etc. Imported both the HAL_BSP and HAL_APP folders using: 'Import NIOS-V CMake Project... In the AshlingRSICFree IDE i can successfully run a 'Build all' and compile the HAL_BSP. BUT When i select the hal_app folder and try to build the Project i get these error messages: 17:37:20 Buildscript generation: hal_app::Default in D:\VAREX_mSGDMA_Eval\software\hal_app\build\Default cmake -DCMAKE_EXPORT_COMPILE_COMMANDS:BOOL=ON -G "Unix Makefiles" "D:\\VAREX_mSGDMA_Eval\\software\\hal_app" CMake Warning: Ignoring extra path from command line: "D:\VAREX_mSGDMA_Eval\software\hal_app" CMake Error: The source directory "D:/VAREX_mSGDMA_Eval/software/hal_app" does not appear to contain CMakeLists.txt. Specify --help for usage, or press the help button on the CMake GUI. Problems : Description Resource Path Location Type CMake Error: The source directory "D:/VAREX_mSGDMA_Eval/software/hal_app" does not appear to contain CMakeLists.txt. hal_app de.marw.cdt.cmake.core.internal.CMakeErrorParser CMake Problem cmake exited with status 1. See CDT global build console for details. hal_app de.marw.cdt.cmake.core.internal.BuildscriptGenerator Buildscript Generation Problem Looking at the hal_bsl folder i can see the CMakeLists.txt is present, it is not present (automatically anyway) in the hal_app folder. I assume it would be if it was part of the BSP generate flow, but it ins't there so i assumed it shouldn't be there (in the hal_app folder i mean). Even if i add it manually then try to do a project build again i then see an error message saying the CmakeCache.txt file has not been created. This seems like a big tools flow mess to me. The Project is automatically setup to use a CMake Compile and CMake Build flow. But its not working. I am trying to use the AshlingRISC IDE GDB Debugger to load my ELF file to the NIOSV processor to allow me to debug my project, but of course because i can't even build it this is impossible. I have tried using niosv cli commands to build my ELF file ...and they seem to work, which means the AshlingRISC IDE is the culprit in the failed IDE build process: Here are my NIOSV cli commands : mSGDMA Test: $ niosv-app --bsp-dir=D:/VAREX_mSGDMA_Eval/software/hal_bsp --app-dir=D:/VAREX_mSGDMA_Eval/software/hal_app --srcs=D:/VAREX_mSGDMA_Eval/software/hal_app/msgdma_loopback.c $ cmake -S D:/VAREX_mSGDMA_Eval/software/hal_app -B D:/VAREX_mSGDMA_Eval/software/hal_app/build -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Debug $ make -j4 -C D:/VAREX_mSGDMA_Eval/software/hal_app/build After i try and fail to do a project build i can also no loner clean this project, it gets stuck in red with the same error. The only way i can get it back to the start state is : File -> Restart ...this is not great !! Does anybody know why i get these errors and how to fix them please ? : Here i have also linked to an older post here in the knowledge base Claiming that "This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4. and later". This appears to be NOT the case though :) Why does CMake Error: The source directory "<project_directory>/intel_niosv_m_0_EXAMPLE_DESIGN" does not contain CMakeLists.txt. when compiling the Nios® V processor application in Command Line Interface? | Altera Community - 338917 NOTE: I have attached 3 screenshots, 2 show the output from the NIOSV CLI when i run the 3 compile commands. The third one shows what happens when i try to load the ELF file which was created after the 3 Compilation steps run to completion. It looks like the GDB debugger detects the NIOSV/m processor (the 1 hard message) and then promptly crashed during part of the boot process. Does anybody have any ideas about why that might be and what is going on please ? Thanks for any help, Dr Barry H303Views0likes9CommentsNIOS2 filesystem support
We have a system running on NIOS 2 processor with Cyclone5 FPGA and ecos RTOS. We are planning to remove the OS dependency and convert the application to baremetal. Already JFFS filesystem and FIS filesystem are being used in the application. Is there any filesystem libraries that can be used in baremetal? Files are having read and write access. Any specifc links to some examples of the usage of the same in NIOS 2 processor?150Views0likes4Comments