Nios® V Processor Installation and Hello World Execution, Part 1
Note: This article is an English translation of this Japanese article. Please refer to the original article for updates. Introduction This article targets those who are new to FPGA, covering the overview, installation, hardware construction, and execution of Hello World for the Nios® V/m embedded processor. Those who already have experience with FPGA may skim through certain parts like the installation. The Operating Systems used for operational verification are as follows: Windows 11 Enterprise Version: 22H2, Build: 22621.2715 Ubuntu 22.04.3 LTS (Jammy Jellyfish), Kernel version: 6.2.0-36-generic The work will primarily be conducted on Linux, and explanations will include actual logs. However, when commands differ significantly on Windows, they will be explained as necessary. Below are reference materials for the Nios® V/m embedded processor: Nios® V Embedded Processor Design Handbook Nios® V Processor Reference Manual NiosV tool setup for Eclipse CDT and OpenOCD 1. Overview of the Nios® V/m Embedded Processor 1.1 Instruction Set The Nios® V/m embedded processor supports the RV32IA instruction set. RV32I denotes a 32-bit integer instruction set, and the symbols following it indicate extensions. The main extensions are listed below. Extension Description M Integer Multiplication and Division A Atomic Instructions F Single-Precision Floating-Point D Double-Precision Floating-Point Q Quad-Precision Floating-Point C Compressed Instructions Therefore, R32IA supports 32-bit integer instructions and atomic instructions. The processor has 32 32-bit wide integer registers, implemented using block memories like M20K. As indicated by the extension symbols, floating-point registers (f0-f31, fcsr) are not implemented. For more details, please refer to RISC-V Unprivileged Spec v.20191213. 1.2 Configuration The basic configuration is shown below. Item Details General Purpose Register file 32-bit width x 32 integer general-purpose register file Arithmetic Logic Unit (ALU) Performs arithmetic, comparison, logical, and shift operations. Also used for generating addresses for loads and stores Control and Status Registers (CSR) Control registers Exception Controller Exception processing controller Interrupt Controller Interrupt controller, level-triggered Instruction Bus Instruction bus Data Bus Data bus RISC-V based Debug Module Debug module Here are the main differences from Nios® II: Item Nios® V/m Embedded Processor Nios® II Bus Arm* ABMA* AXI Avalon-MM Number of Interrupt Terminals 16 32 Debug Open OCD (On-Chip Debugger) compliant Proprietary specification 1.3 Instruction, Data Bus While Nios® II used the Avalon-MM bus, the Nios® V/m Processor has switched to Arm* ABMA* AXI. This change allows for exceptions to be triggered in the Nios® V/m Processor when the response from AXI is not OK. The types of AXI responses are as follows: RESP[1:0] Response Description 2'b00 OKAY Normal access OK 2'b01 EXOKAY Exclusive access OK 2'b10 SLVERR Slave returned an error 2'b11 DECERR No slave at the specified address For more details, please refer to Read and Write Response Structure. 1.4 Pipeline The Nios® V/m embedded processor is a 5-stage pipeline CPU. An overview of each stage is provided below. Stage Denotation Function Instruction Fetch F • PC+4 calculation<br>• Next instruction fetch<br>• Pre-decode for register file read Instruction Decode D • Decode the instruction<br>• Register file read data available<br>• Hazard resolution and data forwarding Instruction Execute E • ALU operations<br>• Memory address calculation<br>• Branch resolution<br>• CSR read/write Memory M • Memory and multicycle operations<br>• Register file write<br>• Branch redirection Write Back W • Facilitates data dependency resolution by providing General Purpose Register value. 1.5 Exceptions The exceptions currently defined are as follows: Exception Description Instruction Address Misaligned Exception is issued when the Program Counter (PC) is not aligned on a 32-bit boundary during the instruction fetch stage (i.e., the lower 2 bits of the PC are not zero). Instruction Access Fault Exception is issued if the AXI response during instruction read is not OKAY. Illegal Instruction Exception is issued if an unimplemented or undefined instruction is detected during instruction decode, or if an unimplemented or undefined CSR access is detected during the execute stage. Breakpoint Exception is issued at the decode stage when a break instruction is executed. Load Address Misaligned<br>Store/AMO Address Misaligned Exception is issued during the memory access stage if the load/store instruction's address is not aligned with the access size. Load Access Fault<br>Store/AMO Access Fault Exception is issued if the AXI bus returns a response other than OKAY during memory access. Environment Call from U-mode Exception is issued when ECALL instruction is executed in U-mode. Environment Call from S-mode Exception is issued when ECALL instruction is executed in S-mode. Environment Call from M-mode Exception is issued when ECALL instruction is executed in M-mode. Instruction Page Fault<br>Load Page Fault<br>Store/AMO Page Fault Exception is issued when accessing a virtual address that does not correspond to a physical address, or when access rights are insufficient. 1.6 CSR Registers The registers mapped in the CSR area are shown below. For more details on the registers, please refer to RISC-V Privileged Spec v.20190608. Register Name Description mvendorid Machine Vendor ID Register marchid Machine Architecture ID Register mimpid Machine Implementation ID Register mhartid Hart ID Register mstatus Machine Status Register mtvec Machine Trap-Vector Base-Address Register mip Machine Interrupt-pending Register mie Machine Interrupt-enable Register mcounteren Machine Counter-enable Register mepc Machine Exception Program Counter mcause Machine Cause Register The registers mapped in the memory-mapped area are shown below. Register Name Description Offset mtimecmp Machine Time Register 0x00 mtime Machine Time Register 0x08 1.7 Supported Devices The FPGA devices currently supported are as follows: Intel® Quartus® Prime Edition Device Family Pro Intel® Cyclone® 10 device Pro Intel® Arria® 10 device Pro Intel® Stratix® 10 device Pro Intel Agilex® 7 device Standard Intel® MAX® 10 Standard Intel® Cyclone® IV E Standard Intel® Cyclone® IV GX Standard Intel® Cyclone® V Standard Intel® Cyclone® 10 LP Standard Intel® Arria® 10 Standard Intel® Arria® II GX Standard Intel® Arria® II GZ Standard Intel® Arria® V Standard Intel® Arria® V GZ Standard Intel® Stratix® IV Standard Intel® Stratix® V 2. Obtaining a License To use the Nios® V/m embedded processor, you need to acquire a free license. This section explains the procedure for obtaining a license. Additionally, we will also obtain a license for Questa*-Intel® FPGA Edition Software, used as a simulator. 2.1 Sign In Click on the Self Service Licensing Center. A Sign In screen like the one below will appear, so please sign in with your Intel account. If you do not have an Intel account, please create one. 2.2 Obtaining a Nios® V/m Embedded Processor License After signing in, the following screen will appear. Select Intel® FPGA IP IP-NIOSVM, enter "1" in "# of Seats", and click "Get License" at the bottom right. 2.3 Registering a New Computer The following screen will appear. If you are obtaining a license for the first time, select "Create a New Computer". If you have already registered, select "Assign an Existing Computer" and click the "Generate" button at the bottom right. This time, we will register a new computer, creating an ID using the Ethernet MAC ID. 2.4 Entering New Computer Information The following screen will appear, where you set up the computer you are using. Enter the necessary items below and click "Generate License". Item Description Computer Name Enter any name License Type Select FIXED Computer Name Select NIC ID Primary Computer ID Enter the PC's Ethernet MAC ID 2.5 Checking the Nios® V/m Embedded Processor License File Once generated, the following screen will appear, and the license file will be sent to the registered email address, so please check the file. 2.6 Obtaining a Questa*-Intel® FPGA Edition Software License Follow the same procedure to obtain a license for Questa*-Intel® FPGA Edition Software. If you already have a license, proceed to the next chapter. As before, click on Self Service Licensing Center. Select Questa*-Intel® FPGA Starter software Edition SW-QUESTA, enter "1" in "# of Seats", and click "Get License" at the bottom right. 2.7 Adding to an Existing Computer If the following screen appears, specify the PC you registered earlier by selecting "Assign an Existing Computer", enter the MAC ID, and press the "Generate" button at the bottom right. 2.8 Checking the Questa*-Intel® FPGA Edition Software License File Once generated, the following screen will appear, and the license file will be sent to the registered email address. With this, the process of obtaining the license is complete. 3. Installation This chapter explains how to download and install Intel® Quartus® Prime Software, and how to set up environment variables. 3.1 Installing Intel® Quartus® Prime Pro Edition 23.3 3.1.1 Download First, click on the FPGA Software Download Center and go to the page below. Follow the instructions for your OS to click on the corresponding version of Intel® Quartus® Prime Software. This explanation will cover installation on Linux. Clicking will bring up the following page. Verify that the version is 23.3, then scroll down. Download the Intel® Quartus® Prime Pro Edition Installer (RUN) from the page below. For Windows, download the Intel® Quartus® Prime Pro Edition Installer (EXE). Once downloaded, enter the following commands in the download directory to launch the installer: $ chmod +x *.run $ ./qinst-linux-23.3-104.run For Windows, double-click the downloaded qint-windows-23.3-104.exe. When the installer launches, select: Intel® Quartus® Prime Pro Edition Part 1 (includes Nios II EDS) Intel® Quartus® Prime Pro Edition Part 2 Questa*-Intel® FPGA and Starter Editions Intel® Arria® 10 device support Ashling RiscFree IDE for Intel® FPGAs Check "Agree to Intel License Agreement" and click Download. If you wish to change the download or installation location, do so on this screen. For Windows, ensure the following are checked under After-install actions: Launch USB Blaster driver installation Launch USB blaster II driver installation Install JTAG Server as a Windows service During download & installation on Windows, the Device Driver Installation Wizard will open for Intel® FPGA Download Cable II (formerly USB Blaster II) and Intel® FPGA Download Cable (formerly USB Blaster), which are necessary for FPGA configuration and debugging the Nios® V/m embedded processor. Please install them. For Linux, follow "1.6. Installing the Intel FPGA Download Cable II Driver on Linux Systems" in the Intel® FPGA Download Cable II User Guide. Install the Intel® FPGA Download Cable (formerly USB Blaster) driver. Click Next. Click Finish. Install the Intel® FPGA Download Cable II (formerly USB Blaster II) driver. Click Next. Click Finish. This is the screen after completing the Quartus installation. With this, the installation of Intel® Quartus® Prime Pro Edition is complete. 3.2 Setting up Environment Variables 3.2.1 Linux Execute the following to set paths to tools and specify the license file. #!/bin/bash export QUARTUS_ROOTDIR="$HOME/intelFPGA_pro/23.3/quartus" export QSYS_ROOTDIR="$QUARTUS_ROOTDIR/../qsys/bin" export SOPC_KIT_NIOS2="${QUARTUS_ROOTDIR}/../nios2eds" # Tools QUARTUS="$QUARTUS_ROOTDIR/bin64" QSYS="$QSYS_ROOTDIR" NIOSV="$QUARTUS_ROOTDIR/../niosv/bin" NIOS2EDS="$QUARTUS_ROOTDIR/../nios2eds/bin" MAKE="$QUARTUS_ROOTDIR/../riscfree/build_tools/bin" CMAKE="$QUARTUS_ROOTDIR/../riscfree/build_tools/cmake/bin" GCC="$QUARTUS_ROOTDIR/../riscfree/toolchain/riscv32-unknown-elf/bin" if [ -d "$QUARTUS_ROOTDIR/../questa_fe" ]; then QSIM="$QUARTUS_ROOTDIR/../questa_fe/bin" elif [ -d "$QUARTUS_ROOTDIR/../questa_fse" ]; then QSIM="$QUARTUS_ROOTDIR/../questa_fse/bin" else echo "Questa not found" fi export PATH="$QUARTUS:$QSYS:$NIOSV:$NIOS2EDS:$MAKE:$CMAKE:$GCC:$QSIM:$PATH" # License files export LM_LICENSE_FILE="$HOME/license/1-V4ICFB_License.dat" export MGLS_LICENSE_FILE="$HOME/license/1-V4ICFB_License.dat" Regarding the license, $HOME/license/1-V4ICFB_License.dat is specified. If you have multiple license files, separate them with ":" in the following two lines: export LM_LICENSE_FILE="$HOME/license/1-V4ICFB_License.dat" export MGLS_LICENSE_FILE="$HOME/license/1-V4ICFB_License.dat" For example: # Example export LM_LICENSE_FILE="$HOME/license/1-V4ICFB_License.dat:$HOME/license/XXX_License.dat" export MGLS_LICENSE_FILE="$HOME/license/1-V4ICFB_License.dat:$HOME/license/XXX_License.dat" 3.2.2 Windows For Windows, use the Nios V Command Shell, so setting the tool paths is not necessary. Only specify the license. Press the Windows key on your keyboard and type "env". Then select "Edit the system environment variables". The following dialog opens, click on "Environment Variables". In the User Environment Variables settings, as shown in the red frame, specify LM_LICENSE_FILE and MGLS_LICENSE_FILE to the license file. If there are multiple files, separate them with ";". After restarting, the setup is complete. 4. Hardware Construction 4.1 Design Sample & Preparation Here, we construct a design using the Nios® V/m embedded processor. Please download the Intel® Arria® 10 FPGA - Nios® V/m Processor based Hello World version 23.3 from the FPGA Design Store. The file name is top.par. Once the download is complete, copy top.par to your work directory. If your work directory is $HOME/ws, then execute: cp $HOME/Downloads/top.par $HOME/ws For Windows, if your work directory is C:\ws, then drag and drop to copy the file. Next, set up the environment variables in Terminal for Linux or launch Nios V Command Shell (Quartus Prime Pro 23.3) from the Start menu in Windows. Move to $HOME/ws and execute the following: quartus top.par & When Quartus launches, it will ask for the location to expand the Example Design. Specify your preferred work directory and click OK. From now on, we will proceed assuming the Example Design is expanded in $HOME/ws/top_project for Linux and C:/ws/top_project for Windows. All terminal commands should be executed from $HOME/ws/top_project or C:/ws/top_project. As you can see in $HOME/ws/top_project/hw/top.v, this design uses only one 50MHz clock input, making it easy to port to other FPGAs. For more details, see 4.5 Porting to Other FPGAs. For the reset, we use an IP that controls signals from JTAG called ISSP (In-System Source & Probe) and perform the reset with toggle_issp.tcl. For more details, see 5.1.6 CPU Reset by ISSP (In-System Source & Probe). File Description readme.txt README file hw/top.qpf Quartus Project file hw/top.qsf Quartus Settings file hw/top.sdc Synopsys Design Constraints file hw/top.v Design TOP RTL file scripts/create_qsys.tcl Platform Designer creation script scripts/toggle_issp.tcl Reset execution script sw/app_hal/hello.c Main file for HAL Hello World sw/app_ucosii/hello_ucosii.c Main file for uC/OS-II Hello World sw/app_freertos/hello_freertos.c Main file for FreeRTOS™ Hello World As a premise, the Example Design just downloaded and expanded is in a ready-to-test state, meaning all files and binaries required for running the Nios® V/m embedded processor are already included. The FPGA configuration file is at $HOME/ws/top_project/ready_to_test/top.sof, and the ELF files for the Nios® V/m embedded processor application are at $HOME/ws/top_project/ready_to_test/app_hal.elf, $HOME/ws/top_project/ready_to_test/app_ucosii.elf, $HOME/ws/top_project/ready_to_test/app_freertos.elf. Use these for testing on actual hardware. The following will explain the steps for compiling the hardware design and building the application for the Nios® V/m embedded processor. 4.2 Checking the Platform Designer Design Let's check the Platform Designer design in the GUI. There are two ways to launch Platform Designer: one is to launch it from the Intel® Quartus® Prime software, and the other is to launch it via command from the Terminal. 4.2.1 Launching Platform Designer from Intel® Quartus® Prime Software Execute the following in the Terminal to launch Quartus: quartus & For Windows, you can also launch Quartus from the Start menu by selecting Quartus Prime Pro Edition 23.3.0.104 -> Quartus (Quartus Prime Pro 23.3). From the File menu, select "Open Project..." and specify $HOME/ws/top_project/hw/top.qpf, then click "Open". From the Tools menu, select "Platform Designer". In the "Open System" dialog that appears, click the red frame and specify the $HOME/ws/top_project/hw/sys.qsys file. Click Open. 4.2.2 Launching Platform Designer from Terminal Move to $HOME/ws/top_project and enter the following command: qsys-edit --quartus-project=hw/top.qpf hw/sys.qsys 4.2.3 Platform Designer Design Here, we'll check the design configuration and settings for each IP. The following is the overall design configuration: 4.2.3.1 Clock This is the configuration screen for the clock input IP. If the input clock differs, change this value. If you change it, also modify the clock period in top.sdc (period is specified in ns). For IP details, please refer to 7.1.1. Clock Bridge Intel® FPGA IP. 4.2.3.2 Reset This is the configuration screen for the reset input IP. For IP details, refer to 6.6.3. Reset Bridge. 4.2.3.3 Nios® V/m Embedded Processor This is the configuration screen for the Nios® V/m embedded processor IP. For details on each parameter, refer to the following: 2.1.1.2.1. Debug Tab 2.1.1.2.2. Use Reset Request Tab 2.1.1.2.3. Vectors Tab 2.1.1.2.4. CPU Architecture 2.1.1.2.5. ECC Tab 4.2.3.4 Internal RAM This is the configuration screen for the internal RAM IP. For details on each parameter, refer to the following: 25.2.1. Memory Type 25.2.2. Size 25.2.3. Read Latency 25.2.4. ROM/RAM Memory Protection 25.2.5. ECC Parameter 4.2.3.5 JTAG UART This is the configuration screen for the JTAG UART IP. For details on each parameter, refer to the following: 12.3.1.1. Write FIFO Settings 12.3.1.2. Read FIFO Settings Once you have confirmed the settings, please close Platform Designer. 4.3 Compiling the Design Next, execute the following command in the Terminal to start compiling the design: quartus_sh --flow compile hw/top Output: Info: ******************************************************************* Info: Running Quartus Prime Shell ... [Output Truncated for Brevity] ... Info: Quartus Prime Shell was successful. 0 errors, 35 warnings Info: Peak virtual memory: 1034 megabytes Info: Processing ended: Mon Nov 27 17:18:51 2023 Info: Elapsed time: 00:02:25 Info: System process ID: 64166 If you look at line 10 in $HOME/ws/top_project/hw/top.qsf: set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files This indicates where the design compilation outputs are stored, and the .sof file is generated in $HOME/ws/top_project/hw/output_files. 4.4 Configuring the FPGA Execute the next command to configure the FPGA. Note that the command slightly differs between Linux and Windows. Linux: quartus_pgm -c 1 -m JTAG -o p\;hw/output_files/top.sof@1 Output: Info: ******************************************************************* Info: Running Quartus Prime Programmer ... [Output Truncated for Brevity] ... Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1917 megabytes Info: Processing ended: Mon Nov 27 17:20:32 2023 Info: Elapsed time: 00:00:13 Info: System process ID: 67118 Windows: quartus_pgm -c 1 -m JTAG -o p;hw/output_files/top.sof@1 Output: Info: ******************************************************************* Info: Running Quartus Prime Programmer ... [Output Truncated for Brevity] ... Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1296 megabytes Info: Processing ended: Tue Nov 28 23:35:04 2023 Info: Elapsed time: 00:00:17 Info: System process ID: 26872 4.5 Porting to Other FPGAs If you are porting this design to other FPGA boards, the main changes will be the device and clock pins. From the Assignments menu, select "Device..." and in the dialog that appears, specify the device you are using. Once the device is changed, Quartus will display "IP update required" in red at the top left. Click "Launch IP Upgrade Tool...". In the dialog that appears, click "Auto Upgrade" to update the IP. Once the IP update is complete and the Status column shows "Success," you can close the dialog. From the Processing menu, select “Start Compilation..." to re-run the compilation. You may encounter errors in the Fitter stage if you haven't set up the clock pin, but you can ignore these for now. From the Assignments menu, select "Pin Planner..." and in the dialog that appears, update the location of the clock pin. Also, update the I/O Standard accordingly. Finally, from the Processing menu, select “Start Compilation..." again and ensure that the compilation runs without errors this time. References Nios® V processor Boot, Simulation, and Debug Edition Nios® V Embedded Processor Design Handbook Nios® V Processor Reference Manual NiosV tool setup for Eclipse CDT and OpenOCD RISC-V Unprivileged Spec v.20191213 RISC-V Privileged Spec v.20190608 RISC-V External Debug Support v.0.13.2 AMBA AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite ACE and ACE-Lite Notices & Disclaimers Intel technologies may require enabled hardware, software, or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from the course of performance, course of dealing, or usage in trade. Nios is a trademark of Intel Corporation or its subsidiaries.
Is it possible to run NIOSV through SDRAM ?
Hello, I am developing a project where NIOS II needs to replaced with NIOSV processor. When my design was having NIOS II as CPU, I was running the software code through External SDRAM on the Cyclone IV E Kit(EP4CE40F23C8). It's working fine with NIOS II. Able to run the software program. Now, when I replaced the NIOS II processor with the NIOSV processor, I am not getting the expected results. I am trying to print a Simple "Hello World" code through the NIOSV processor with the same configuration of design. Almost all BSP settings are same for NIOSV processor as of the NIOS II. Still not getting the results. When running the NIOSV from On-Chip-Ram, everything works as expected, but when I try to run the NIOSV through external SDRAM, the code does not gets executed as expected. I want to inquire that if we can run the NIOSV processor through external SDRAM or not ? Please note that I am not talking here about booting the NIOSV. I am simply running the software image through RiscFree IDE software on the external SDRAM of the board. Regards, Himanshu
NIOS2 doesn't automatically run from external RAM, how to debug
I really need my NIOS2 to autostart and run from off chip RAM using the bootloader copy method. The trouble is that despite many readings of the handbook and multiple rebuilds of the design the code only runs if I start it from Eclipse. How do I debug what I've done wrong? The hardware is the Trenz CYC1000 board which has an EP10CE25 fitted.
Is HW breakpoint required for SW breakpoint ?
Hi, I am trying to add breakpoints to my Nios II Eclipse debug session. My HW system has not defined any HW breakpoints or Data break points (both explicitly set to 0) in Quartus Platform Design stage. Data triggers also set to 0. Trace type "none". Jtag debug included, but debugreq and debugack signals NOT included. In BSP settings: Allow code at reset is enabled. alt_load() is enabled. There's NO rodata or rwdata copy selected for alt_load() during alt_main(). bsp_cflags_debug has option "-g" enabled. OC ram only has reset and exceptions [via alt_load()]. All of my .text and other code is in Off Chip ddr2 RAM. The code is executed from this Off chip RAM. Reset vector however, points to OC ram which has reset, followed by exceptions. When I try to add a breakpoint, the debug perspective shows errors. "cannot access memory at <address> " and "failed to add breakpoint". The <address> to be accessed is in the Off chip RAM location. The code flow only stops once at main() and that's it. From all the documentation, forum search and literature, I could not figure out why this error occurs. The address location in memory is off chip RAM but is R/W (volatile). Hence theoretically, the debugger should be able to insert a software breakpoint instruction. I am NOT debugging boot code and whatever code is present is in R/W memory. In all the user guides, sw dev handbook, embedded handbook and the IP guide, it is stated that HW breakpoints are needed for boot code debug (non volatile memory, instructions cannot be inserted/overwritten. If HW breakpoints are needed for SW breakpoints, I have not found it in literature. Of course, there's something else, since the breakpoint is not set. What am I missing (even theoretically)? Any other setting(s) to check/set ? Unfortunately, cannot share any files. Thanks in advance ! Edit 1 - HW is Cyclone 5 Edit 2 - updated Off Chip RAM as volatile in descriptionNios® V Processor Installation and Hello World Execution, Part 2
Note: This is a continuation of Nios® V Processor Installation and Hello World Execution, Part 1 5. Software Construction & Execution The current types of Board Support Packages (BSP) available are hal, ucosii, and freertos. I will introduce the steps for generating, building, and executing each BSP. 5.1 HAL Version 5.1.1 Generating the Board Support Package (BSP) For generating the BSP, specify hal with the --type option in the BSP generation command. Please enter the following command: niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/sys.qsys --type=hal sw/bsp_hal/settings.bsp Output: 2023.11.27.17:21:26 Info: Searching for BSP components with category: os_software_element 2023.11.27.17:21:27 Info: Creating BSP settings. 2023.11.27.17:21:27 Info: Searching for BSP components with category: driver_element 2023.11.27.17:21:27 Info: Searching for BSP components with category: software_package_element 2023.11.27.17:21:27 Info: Loading drivers from ensemble report. 2023.11.27.17:21:27 Info: Finished loading drivers from ensemble report. 2023.11.27.17:21:27 Info: Evaluating default script "/home/ubuntu_usr/intelFPGA_pro/23.3/quartus/../niosv/scripts/bsp-defaults/bsp-set-defaults.tcl". 2023.11.27.17:21:27 Info: Tcl message: "STDIO character device is jtag_uart" 2023.11.27.17:21:27 Info: Tcl message: "System timer device is cpu" 2023.11.27.17:21:27 Info: Tcl message: "Default linker sections mapped to ram" 2023.11.27.17:21:27 Info: Tcl message: "No bootloader located at the reset address." 2023.11.27.17:21:27 Info: Tcl message: "Application ELF allowed to contain code at the reset address." 2023.11.27.17:21:27 Info: Tcl message: "The alt_load() facility is enabled." 2023.11.27.17:21:27 Info: Tcl message: "The .rwdata section is copied into RAM by alt_load()." 2023.11.27.17:21:28 Info: Saving BSP settings file. 2023.11.27.17:21:28 Info: Default memory regions will not be persisted in BSP Settings File. 2023.11.27.17:21:28 Info: Generated file "/home/ubuntu_usr/ws/ws_pro/niosv_hello_world/top_project/sw/bsp_hal/settings.bsp" 2023.11.27.17:21:28 Info: Generating BSP files in "/home/ubuntu_usr/ws/ws_pro/niosv_hello_world/top_project/sw/bsp_hal" 2023.11.27.17:21:28 Info: Default memory regions will not be persisted in BSP Settings File. 2023.11.27.17:21:28 Info: Generated file "/home/ubuntu_usr/ws/ws_pro/niosv_hello_world/top_project/sw/bsp_hal/settings.bsp" 2023.11.27.17:21:28 Info: Finished generating BSP files. Total time taken = 2 seconds 5.1.2 Generating CMafileLists.txt Execute the following command to generate the CMafileLists.txt required for compiling the application. If the source file specified in --srcs is not present in the path, an error will occur. niosv-app --bsp-dir=sw/bsp_hal --app-dir=sw/app_hal --srcs=sw/app_hal --elf-name=hello.elf Output: 2023.11.27.17:23:52 Info: Elf name is set to "hello.elf". 2023.11.27.17:23:52 Info: Source file "hello.c" added from directory "sw/app_hal". 2023.11.27.17:23:52 Info: "sw/app_hal/CMakeLists.txt" was generated. 5.1.3 Generating MakeFile Execute the following command to generate MakeFile from CMakeLists.txt. Since we are specifying the existing directory sw/app_hal/build as the build directory, you need to delete sw/app_hal/build/CMakeCache.txt first. rm sw/app_hal/build/CMakeCache.txt Then generate the MakeFile. cmake -S sw/app_hal -G "Unix Makefiles" -B sw/app_hal/build Output: -- Defaulting build type to Debug. -- The ASM compiler identification is GNU -- Found assembler: /home/ubuntu_usr/intelFPGA_pro/23.3/riscfree/toolchain/riscv32-unknown-elf/bin/riscv32-unknown-elf-gcc -- The C compiler identification is GNU 12.1.0 -- Detecting C compiler ABI info -- Detecting C compiler ABI info - done -- Check for working C compiler: /home/ubuntu_usr/intelFPGA_pro/23.3/riscfree/toolchain/riscv32-unknown-elf/bin/riscv32-unknown-elf-gcc - skipped -- Detecting C compile features -- Detecting C compile features - done -- The CXX compiler identification is GNU 12.1.0 -- Detecting CXX compiler ABI info -- Detecting CXX compiler ABI info - done -- Check for working CXX compiler: /home/ubuntu_usr/intelFPGA_pro/23.3/riscfree/toolchain/riscv32-unknown-elf/bin/riscv32-unknown-elf-g++ - skipped -- Detecting CXX compile features -- Detecting CXX compile features - done -- Configuring done (0.4s) -- Generating done (0.0s) -- Build files have been written to: /home/ubuntu_usr/ws/ws_pro/niosv_hello_world/top_project/sw/app_hal/build 5.1.4 Generating hello.elf Execute the following command to generate hello.elf. make -C sw/app_hal/build Output: make: Entering directory '/home/ubuntu_usr/ws/ws_pro/niosv_hello_world/top_project/sw/app_hal/build' [ 1%] Building ASM object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_log_macro.S.obj [ 2%] Building ASM object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_mcount.S.obj [ 3%] Building ASM object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/crt0.S.obj [ 4%] Building ASM object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/machine_trap.S.obj [ 5%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_alarm_start.c.obj [ 6%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_busy_sleep.c.obj [ 7%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_close.c.obj [ 8%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_dcache_flush.c.obj [ 9%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_dcache_flush_all.c.obj [ 10%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_dcache_flush_no_writeback.c.obj [ 12%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_dev.c.obj [ 13%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_dev_llist_insert.c.obj [ 14%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_dma_rxchan_open.c.obj [ 15%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_dma_txchan_open.c.obj [ 16%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_do_ctors.c.obj [ 17%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_do_dtors.c.obj [ 18%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_env_lock.c.obj [ 19%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_environ.c.obj [ 20%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_errno.c.obj [ 21%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_execve.c.obj [ 23%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_exit.c.obj [ 24%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_fcntl.c.obj [ 25%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_fd_lock.c.obj [ 26%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_fd_unlock.c.obj [ 27%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_find_dev.c.obj [ 28%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_find_file.c.obj [ 29%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_flash_dev.c.obj [ 30%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_fork.c.obj [ 31%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_fs_reg.c.obj [ 32%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_fstat.c.obj [ 34%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_get_fd.c.obj [ 35%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_getchar.c.obj [ 36%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_getpid.c.obj [ 37%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_gettod.c.obj [ 38%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_gmon.c.obj [ 39%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_icache_flush.c.obj [ 40%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_icache_flush_all.c.obj [ 41%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_iic.c.obj [ 42%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_iic_isr_register.c.obj [ 43%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_instruction_exception_register.c.obj [ 45%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_io_redirect.c.obj [ 46%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_ioctl.c.obj [ 47%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_irq_handler.c.obj [ 48%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_isatty.c.obj [ 49%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_kill.c.obj [ 50%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_link.c.obj [ 51%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_load.c.obj [ 52%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_log_printf.c.obj [ 53%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_lseek.c.obj [ 54%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_main.c.obj [ 56%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_malloc_lock.c.obj [ 57%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_open.c.obj [ 58%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_printf.c.obj [ 59%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_putchar.c.obj [ 60%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_putcharbuf.c.obj [ 61%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_putstr.c.obj [ 62%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_read.c.obj [ 63%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_release_fd.c.obj [ 64%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_remap_cached.c.obj [ 65%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_remap_uncached.c.obj [ 67%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_rename.c.obj [ 68%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_sbrk.c.obj [ 69%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_settod.c.obj [ 70%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_stat.c.obj [ 71%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_tick.c.obj [ 72%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_times.c.obj [ 73%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_tls.c.obj [ 74%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_uncached_free.c.obj [ 75%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_uncached_malloc.c.obj [ 76%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_unlink.c.obj [ 78%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_usleep.c.obj [ 79%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_wait.c.obj [ 80%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/alt_write.c.obj [ 81%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/intel_fpga_api_cmn_dfl.c.obj [ 82%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/intel_fpga_api_cmn_inf.c.obj [ 83%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/intel_fpga_api_cmn_msg.c.obj [ 84%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/intel_fpga_api_niosv.c.obj [ 85%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/intel_fpga_platform_api_niosv.c.obj [ 86%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/intel_niosv_irq.c.obj [ 87%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/HAL/src/mtimer.c.obj [ 89%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/alt_sys_init.c.obj [ 90%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/drivers/src/altera_avalon_jtag_uart_fd.c.obj [ 91%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/drivers/src/altera_avalon_jtag_uart_init.c.obj [ 92%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/drivers/src/altera_avalon_jtag_uart_ioctl.c.obj [ 93%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/drivers/src/altera_avalon_jtag_uart_read.c.obj [ 94%] Building C object bsp_hal/CMakeFiles/hal2_bsp.dir/drivers/src/altera_avalon_jtag_uart_write.c.obj [ 95%] Linking C static library libhal2_bsp.a [ 95%] Built target hal2_bsp [ 96%] Building C object CMakeFiles/hello.elf.dir/hello.c.obj [ 97%] Linking C executable hello.elf [ 97%] Built target hello.elf [ 98%] Creating hello.elf.objdump. [ 98%] Built target create-objdump [100%] Reporting memory available for stack + heap in hello.elf. hello.elf * 110.77 KB - Program size (code + initialized data). * 138.26 KB - Free for stack + heap. [100%] Built target niosv-stack-report make: Leaving directory '/home/ubuntu_usr/ws/ws_pro/niosv_hello_world/top_project/sw/app_hal/build' 5.1.5 Downloading the hello.elf File Download the created ELF file to the target's RAM using the following command. niosv-download sw/app_hal/build/hello.elf Output: INFO: Generating OpenOCD config file. Running "openocd-cfg-gen /tmp/tmpr4uqn_43/niosv.cfg". /bin/bash: /home/ubuntu_usr/intelFPGA_pro/23.3/niosv/bin/../../quartus/linux64/libtinfo.so.6: no version information available (required by /bin/bash) INFO: Starting OpenOCD. Running "openocd -c tcl_port disabled -c gdb_port 0 -c telnet_port 0 -f /tmp/tmpr4uqn_43/niosv.cfg". [OpenOCD output] Open On-Chip Debugger 0.11.0-R22.4 [OpenOCD output] Licensed under GNU GPL v2 [OpenOCD output] For bug reports, read [OpenOCD output] http://openocd.org/doc/doxygen/bugs.html [OpenOCD output] Info : only one transport option; autoselect 'jtag' [OpenOCD output] Info : Application name is OpenOCD.20231127172750 [OpenOCD output] Info : Attempting to find 'USB-BlasterII [1-6.1]' [OpenOCD output] [OpenOCD output] Info : Cable 1: device_name=(null), hw_name=USB-BlasterII, server=(null), port=1-6.1, chain_id=0x55ca56909410, persistent_id=1, chain_type=1, features=2048, server_version_info=(null) [OpenOCD output] Info : TAP position 0 (2E050DD) has 3 SLD nodes [OpenOCD output] Info : node 0 idcode=00486E00 position_n=0 [OpenOCD output] Info : node 1 idcode=08986E00 position_n=0 [OpenOCD output] Info : node 2 idcode=0C006E00 position_n=0 [OpenOCD output] Info : TAP position 1 (4BA00477) has 0 SLD nodes [OpenOCD output] Info : Discovered 2 TAP devices [OpenOCD output] Info : Detected device (tap_position=0) device_id=02e050dd, instruction_length=10, features=4, device_name=10AS066H(1|2|3|3E2|4|4E2)/.. [OpenOCD output] Info : Found an Intel device at tap_position 0.Currently assuming it is SLD Hub [OpenOCD output] Info : Detected device (tap_position=1) device_id=4ba00477, instruction_length=4, features=0, device_name=SOCVHPS [OpenOCD output] Info : Found a ARM device at tap_position 1. Currently assume it is JTAG-DP capable [OpenOCD output] Info : This adapter doesn't support configurable speed [OpenOCD output] Info : JTAG tap: tap_02E050DD.0 tap/device found: 0x02e050dd (mfg: 0x06e (Altera), part: 0x2e05, ver: 0x0) [OpenOCD output] Info : JTAG tap: tap_4BA00477.0 tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) [OpenOCD output] Info : JTAG tap: tap_02E050DD.0 Parent Tap found: 0x02e050dd (mfg: 0x06e (Altera), part: 0x2e05, ver: 0x0) [OpenOCD output] Info : Virtual Tap/SLD node 0x08986E00 found at tap position 0 vtap position 1 [OpenOCD output] Info : datacount=2 progbufsize=8 [OpenOCD output] Info : Examined RISC-V core; found 1 harts [OpenOCD output] Info : hart 0: XLEN=32, misa=0x40000101 [OpenOCD output] Info : starting gdb server for tap_02E050DD.0.niosv_0.cpu on 0 [OpenOCD output] Info : Listening on port 38223 for gdb connections INFO: Found gdb port 38223 [OpenOCD output] Ready for Remote Connections [OpenOCD output] Info : tcl server disabled [OpenOCD output] Info : Listening on port 46631 for telnet connections INFO: Found telnet port 46631 INFO: OpenOCD is ready. INFO: Loading image via GDB. Running "riscv32-unknown-elf-gdb -batch -ex set arch riscv:rv32 -ex set remotetimeout 60 -ex target extended-remote localhost:38223 -ex load sw/app_hal/build/hello.elf -ex set $mstatus &= ~(0x00000088)". The target architecture is set to "riscv:rv32". warning: No executable has been specified and target does not support determining executable automatically. Try using the "file" command. 0x00000008 in ?? () Loading section .entry, size 0x20 lma 0x0 Loading section .exceptions, size 0x29c lma 0x20 Loading section .text, size 0x18c0c lma 0x2bc Loading section .rodata, size 0xf60 lma 0x18ed0 Loading section .rwdata, size 0x1bd8 lma 0x1ba08 Start address 0x0000036c, load size 113152 Transfer rate: 186 KB/sec, 10286 bytes/write. [Inferior 1 (Remote target) detached] 5.1.6 Resetting the CPU by ISSP (In-System Source & Probe) As explained during the design creation, the reset signal in this design is connected to ISSP. Reset the design by toggling the reset signal through ISSP. For more information about ISSP, refer to 2.3.1. In-System Sources and Probes. Execute the following command to reset the design. quartus_stp -t scripts/toggle_issp.tcl Output: Info: ******************************************************************* Info: Running Quartus Prime Signal Tap Info: Version 23.3.0 Build 104 09/20/2023 SC Pro Edition Info: Copyright (C) 2023 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the Intel FPGA Software License Subscription Agreements Info: on the Quartus Prime software download page. Info: Processing started: Mon Nov 27 17:28:43 2023 Info: System process ID: 69244 Info: Command: quartus_stp -t scripts/toggle_issp.tcl Info: The application is running in 'DNI' mode. Info (23030): Evaluation of Tcl script scripts/toggle_issp.tcl was successful Info: Quartus Prime Signal Tap was successful. 0 errors, 0 warnings Info: Peak virtual memory: 737 megabytes Info: Processing ended: Mon Nov 27 17:28:44 2023 Info: Elapsed time: 00:00:01 Info: System process ID: 69244 5.1.7 Displaying "Hello world" on the Terminal Execute the following command to display messages from the JTAG-UART implemented in the design on the host terminal. The JTAG-UART waits until communication with the host is established, so you can confirm that the messages start from the beginning. Press "CTRL+C" to exit. juart-terminal Output: juart-terminal: connected to hardware target using JTAG UART on cable juart-terminal: "USB-BlasterII [1-6.1]", device 1, instance 0 juart-terminal: (Use the IDE stop button or Ctrl-C to terminate) Hello world, this is the Nios V/m cpu checking in 0... Hello world, this is the Nios V/m cpu checking in 1... Hello world, this is the Nios V/m cpu checking in 2... Hello world, this is the Nios V/m cpu checking in 3... Hello world, this is the Nios V/m cpu checking in 4... Hello world, this is the Nios V/m cpu checking in 5... ..... ..... ..... Hello world, this is the Nios V/m cpu checking in 995... Hello world, this is the Nios V/m cpu checking in 996... Hello world, this is the Nios V/m cpu checking in 997... Hello world, this is the Nios V/m cpu checking in 998... Hello world, this is the Nios V/m cpu checking in 999... Bye world! juart-terminal: exiting due to ^C on host 5.2 uC/OS-II Edition Next, we will compile and execute the uC/OS-II sample. 5.2.1 Generating Board Support Package (BSP) Use the following command to generate a BSP for uC/OS-II. The BSP settings file sw/bsp_ucosii/settings.bsp is prepared. Specify ucosii for the Type. niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/sys.qsys --type=ucosii sw/bsp_ucosii/settings.bsp Output: 2023.11.28.00:33:30 Info: Searching for BSP components with category: os_software_element 2023.11.28.00:33:31 Info: Creating BSP settings. 2023.11.28.00:33:31 Info: Searching for BSP components with category: driver_element 2023.11.28.00:33:31 Info: Searching for BSP components with category: software_package_element 2023.11.28.00:33:31 Info: Loading drivers from ensemble report. 2023.11.28.00:33:31 Info: Finished loading drivers from ensemble report. 2023.11.28.00:33:31 Info: Evaluating default script "/home/ubuntu_usr/intelFPGA_pro/23.3/quartus/../niosv/scripts/bsp-defaults/bsp-set-defaults.tcl". 2023.11.28.00:33:31 Info: Tcl message: "STDIO character device is jtag_uart" 2023.11.28.00:33:31 Info: Tcl message: "System timer device is cpu" 2023.11.28.00:33:31 Info: Tcl message: "Default linker sections mapped to ram" 2023.11.28.00:33:31 Info: Tcl message: "No bootloader located at the reset address." 2023.11.28.00:33:31 Info: Tcl message: "Application ELF allowed to contain code at the reset address." 2023.11.28.00:33:31 Info: Tcl message: "The alt_load() facility is enabled." 2023.11.28.00:33:31 Info: Tcl message: "The .rwdata section is copied into RAM by alt_load()." 2023.11.28.00:33:31 Info: Saving BSP settings file. 2023.11.28.00:33:31 Info: Default memory regions will not be persisted in BSP Settings File. 2023.11.28.00:33:31 Info: Generated file "/home/ubuntu_usr/ws/ws_pro/niosv_hello_world/top_project/sw/bsp_ucosii/settings.bsp" 2023.11.28.00:33:31 Info: Generating BSP files in "/home/ubuntu_usr/ws/ws_pro/niosv_hello_world/top_project/sw/bsp_ucosii" 2023.11.28.00:33:31 Info: Default memory regions will not be persisted in BSP Settings File. 2023.11.28.00:33:31 Info: Generated file "/home/ubuntu_usr/ws/ws_pro/niosv_hello_world/top_project/sw/bsp_ucosii/settings.bsp" 2023.11.28.00:33:31 Info: Finished generating BSP files. Total time taken = 2 seconds 5.2.2 Generating CMafileLists.txt Generate CMakefileLists.txt. The application directory and source code for uC/OS-II are available in sw/app_ucosii. niosv-app --bsp-dir=sw/bsp_ucosii --app-dir=sw/app_ucosii --srcs=sw/app_ucosii --elf-name=hello_ucosii.elf Output: 2023.11.28.00:56:14 Info: Elf name is set to "hello_ucosii.elf". 2023.11.28.00:56:14 Info: Source file "hello_ucosii.c" added from directory "sw/app_ucosii". 2023.11.28.00:56:14 Info: "sw/app_ucosii/CMakeLists.txt" was generated. 5.2.3 Generating Makefile Execute the following command to generate a Makefile from CMakeLists.txt. cmake -S sw/app_ucosii -G "Unix Makefiles" -B sw/app_ucosii/build Output: -- Defaulting build type to Debug. -- The ASM compiler identification is GNU -- Found assembler: /home/ubuntu_usr/intelFPGA_pro/23.3/riscfree/toolchain/riscv32-unknown-elf/bin/riscv32-unknown-elf-gcc -- The C compiler identification is GNU 12.1.0 -- Detecting C compiler ABI info -- Detecting C compiler ABI info - done -- Check for working C compiler: /home/ubuntu_usr/intelFPGA_pro/23.3/riscfree/toolchain/riscv32-unknown-elf/bin/riscv32-unknown-elf-gcc - skipped -- Detecting C compile features -- Detecting C compile features - done -- The CXX compiler identification is GNU 12.1.0 -- Detecting CXX compiler ABI info -- Detecting CXX compiler ABI info - done -- Check for working CXX compiler: /home/ubuntu_usr/intelFPGA_pro/23.3/riscfree/toolchain/riscv32-unknown-elf/bin/riscv32-unknown-elf-g++ - skipped -- Detecting CXX compile features -- Detecting CXX compile features - done -- Configuring done (0.2s) -- Generating done (0.0s) -- Build files have been written to: /home/ubuntu_usr/ws/ws_pro/niosv_hello_world/top_project/sw/app_ucosii/build 5.2.4 Generating hello_ucosii.elf Execute the following command to generate hello_ucosii.elf. make -C sw/app_ucosii/build Output: make: Entering directory '/home/ubuntu_usr/ws/ws_pro/niosv_hello_world/top_project/sw/app_ucosii/build' [ 1%] Building ASM object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_log_macro.S.obj [ 2%] Building ASM object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_mcount.S.obj [ 3%] Building ASM object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/crt0.S.obj [ 4%] Building ASM object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/machine_trap.S.obj [ 5%] Building ASM object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/os_cpu_a.S.obj [ 6%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_alarm_start.c.obj [ 7%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_busy_sleep.c.obj [ 8%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_close.c.obj [ 9%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_dcache_flush.c.obj [ 10%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_dcache_flush_all.c.obj [ 11%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_dcache_flush_no_writeback.c.obj [ 12%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_dev.c.obj [ 13%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_dev_llist_insert.c.obj [ 14%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_dma_rxchan_open.c.obj [ 15%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_dma_txchan_open.c.obj [ 16%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_do_ctors.c.obj [ 17%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_do_dtors.c.obj [ 17%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_environ.c.obj [ 18%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_errno.c.obj [ 19%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_execve.c.obj [ 20%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_exit.c.obj [ 21%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_fcntl.c.obj [ 22%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_fd_lock.c.obj [ 23%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_fd_unlock.c.obj [ 24%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_find_dev.c.obj [ 25%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_find_file.c.obj [ 26%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_flash_dev.c.obj [ 27%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_fork.c.obj [ 28%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_fs_reg.c.obj [ 29%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_fstat.c.obj [ 30%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_get_fd.c.obj [ 31%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_getchar.c.obj [ 32%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_getpid.c.obj [ 33%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_gettod.c.obj [ 34%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_gmon.c.obj [ 35%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_icache_flush.c.obj [ 36%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_icache_flush_all.c.obj [ 37%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_iic.c.obj [ 37%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_iic_isr_register.c.obj [ 38%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_instruction_exception_register.c.obj [ 39%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_io_redirect.c.obj [ 40%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_ioctl.c.obj [ 41%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_irq_handler.c.obj [ 42%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_isatty.c.obj [ 43%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_kill.c.obj [ 44%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_link.c.obj [ 45%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_load.c.obj [ 46%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_log_printf.c.obj [ 47%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_lseek.c.obj [ 48%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_main.c.obj [ 49%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_open.c.obj [ 50%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_printf.c.obj [ 51%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_putchar.c.obj [ 52%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_putcharbuf.c.obj [ 53%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_putstr.c.obj [ 54%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_read.c.obj [ 55%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_release_fd.c.obj [ 56%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_remap_cached.c.obj [ 57%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_remap_uncached.c.obj [ 57%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_rename.c.obj [ 58%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_sbrk.c.obj [ 59%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_settod.c.obj [ 60%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_stat.c.obj [ 61%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_tick.c.obj [ 62%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_times.c.obj [ 63%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_tls.c.obj [ 64%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_uncached_free.c.obj [ 65%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_uncached_malloc.c.obj [ 66%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_unlink.c.obj [ 67%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_usleep.c.obj [ 68%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_wait.c.obj [ 69%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/alt_write.c.obj [ 70%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/intel_fpga_api_cmn_dfl.c.obj [ 71%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/intel_fpga_api_cmn_inf.c.obj [ 72%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/intel_fpga_api_cmn_msg.c.obj [ 73%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/intel_fpga_api_niosv.c.obj [ 74%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/intel_fpga_platform_api_niosv.c.obj [ 75%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/intel_niosv_irq.c.obj [ 76%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/mtimer.c.obj [ 77%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/HAL/src/os_cpu_c.c.obj [ 77%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/UCOSII/src/alt_env_lock.c.obj [ 78%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/UCOSII/src/alt_malloc_lock.c.obj [ 79%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/UCOSII/src/os_core.c.obj [ 80%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/UCOSII/src/os_dbg_r.c.obj [ 81%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/UCOSII/src/os_flag.c.obj [ 82%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/UCOSII/src/os_mbox.c.obj [ 83%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/UCOSII/src/os_mem.c.obj [ 84%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/UCOSII/src/os_mutex.c.obj [ 85%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/UCOSII/src/os_q.c.obj [ 86%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/UCOSII/src/os_sem.c.obj [ 87%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/UCOSII/src/os_task.c.obj [ 88%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/UCOSII/src/os_time.c.obj [ 89%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/UCOSII/src/os_tmr.c.obj [ 90%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/UCOSII/src/ucos_ii.c.obj [ 91%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/alt_sys_init.c.obj [ 92%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/drivers/src/altera_avalon_jtag_uart_fd.c.obj [ 93%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/drivers/src/altera_avalon_jtag_uart_init.c.obj [ 94%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/drivers/src/altera_avalon_jtag_uart_ioctl.c.obj [ 95%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/drivers/src/altera_avalon_jtag_uart_read.c.obj [ 96%] Building C object bsp_ucosii/CMakeFiles/ucosii_hal2_bsp.dir/drivers/src/altera_avalon_jtag_uart_write.c.obj [ 97%] Linking C static library libucosii_hal2_bsp.a [ 97%] Built target ucosii_hal2_bsp [ 97%] Building C object CMakeFiles/app_ucosii.elf.dir/hello_ucosii.c.obj [ 98%] Linking C executable app_ucosii.elf [ 98%] Built target app_ucosii.elf [ 99%] Creating app_ucosii.elf.objdump. [ 99%] Built target create-objdump [100%] Reporting memory available for stack + heap in app_ucosii.elf. app_ucosii.elf * 186.04 KB - Program size (code + initialized data). * 62.98 KB - Free for stack + heap. [100%] Built target niosv-stack-report make: Leaving directory '/home/ubuntu_usr/ws/ws_pro/niosv_hello_world/top_project/sw/app_ucosii/build' 5.2.5 Downloading hello_ucosii.elf File Next, download the created ELF file to the target's RAM using the following command. niosv-download sw/app_ucosii/build/hello_ucosii.elf Output: INFO: Generating OpenOCD config file. Running "openocd-cfg-gen /tmp/tmp9eayfe_7/niosv.cfg". INFO: Starting OpenOCD. Running "openocd -c tcl_port disabled -c gdb_port 0 -c telnet_port 0 -f /tmp/tmp9eayfe_7/niosv.cfg". [OpenOCD output] Open On-Chip Debugger 0.11.0-R22.4 [OpenOCD output] Licensed under GNU GPL v2 [OpenOCD output] For bug reports, read [OpenOCD output] http://openocd.org/doc/doxygen/bugs.html [OpenOCD output] Info : only one transport option; autoselect 'jtag' [OpenOCD output] Info : Application name is OpenOCD.20231128010450 [OpenOCD output] Info : Attempting to find 'USB-BlasterII [1-6.1]' [OpenOCD output] [OpenOCD output] Info : Cable 1: device_name=(null), hw_name=USB-BlasterII, server=(null), port=1-6.1, chain_id=0x555c3bd47420, persistent_id=1, chain_type=1, features=2048, server_version_info=(null) [OpenOCD output] Info : TAP position 0 (2E050DD) has 3 SLD nodes [OpenOCD output] Info : node 0 idcode=00486E00 position_n=0 [OpenOCD output] Info : node 1 idcode=08986E00 position_n=0 [OpenOCD output] Info : node 2 idcode=0C006E00 position_n=0 [OpenOCD output] Info : TAP position 1 (4BA00477) has 0 SLD nodes [OpenOCD output] Info : Discovered 2 TAP devices [OpenOCD output] Info : Detected device (tap_position=0) device_id=02e050dd, instruction_length=10, features=4, device_name=10AS066H(1|2|3|3E2|4|4E2)/.. [OpenOCD output] Info : Found an Intel device at tap_position 0.Currently assuming it is SLD Hub [OpenOCD output] Info : Detected device (tap_position=1) device_id=4ba00477, instruction_length=4, features=0, device_name=SOCVHPS [OpenOCD output] Info : Found a ARM device at tap_position 1. Currently assume it is JTAG-DP capable [OpenOCD output] Info : This adapter doesn't support configurable speed [OpenOCD output] Info : JTAG tap: tap_02E050DD.0 tap/device found: 0x02e050dd (mfg: 0x06e (Altera), part: 0x2e05, ver: 0x0) [OpenOCD output] Info : JTAG tap: tap_4BA00477.0 tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) [OpenOCD output] Info : JTAG tap: tap_02E050DD.0 Parent Tap found: 0x02e050dd (mfg: 0x06e (Altera), part: 0x2e05, ver: 0x0) [OpenOCD output] Info : Virtual Tap/SLD node 0x08986E00 found at tap position 0 vtap position 1 [OpenOCD output] Info : datacount=2 progbufsize=8 [OpenOCD output] Info : Examined RISC-V core; found 1 harts [OpenOCD output] Info : hart 0: XLEN=32, misa=0x40000101 [OpenOCD output] Info : starting gdb server for tap_02E050DD.0.niosv_0.cpu on 0 [OpenOCD output] Info : Listening on port 46563 for gdb connections INFO: Found gdb port 46563 [OpenOCD output] Ready for Remote Connections [OpenOCD output] Info : tcl server disabled [OpenOCD output] Info : Listening on port 33965 for telnet connections INFO: Found telnet port 33965 INFO: OpenOCD is ready. INFO: Loading image via GDB. Running "riscv32-unknown-elf-gdb -batch -ex set arch riscv:rv32 -ex set remotetimeout 60 -ex target extended-remote localhost:46563 -ex load sw/app_ucosii/build/hello_ucosii.elf -ex set $mstatus &= ~(0x00000088)". The target architecture is set to "riscv:rv32". warning: No executable has been specified and target does not support determining executable automatically. Try using the "file" command. 0x00000000 in ?? () Loading section .entry, size 0x20 lma 0x0 Loading section .exceptions, size 0x29c lma 0x20 Loading section .text, size 0x22ef4 lma 0x2bc Loading section .rodata, size 0x1128 lma 0x231b0 Loading section .rwdata, size 0x1bf0 lma 0x25ec8 Start address 0x00000614, load size 155336 Transfer rate: 146 KB/sec, 11095 bytes/write. [Inferior 1 (Remote target) detached] 5.2.6 Resetting the CPU with ISSP (In-System Source & Probe) Execute the following command to toggle the reset signal and reset the design. quartus_stp -t scripts/toggle_issp.tcl Output: Info: ******************************************************************* Info: Running Quartus Prime Signal Tap Info: Version 23.3.0 Build 104 09/20/2023 SC Pro Edition Info: Copyright (C) 2023 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the Intel FPGA Software License Subscription Agreements Info: on the Quartus Prime software download page. Info: Processing started: Tue Nov 28 01:06:33 2023 Info: System process ID: 10957 Info: Command: quartus_stp -t scripts/toggle_issp.tcl Info: The application is running in 'DNI' mode. Info (23030): Evaluation of Tcl script scripts/toggle_issp.tcl was successful Info: Quartus Prime Signal Tap was successful. 0 errors, 0 warnings Info: Peak virtual memory: 737 megabytes Info: Processing ended: Tue Nov 28 01:06:34 2023 Info: Elapsed time: 00:00:01 Info: System process ID: 10957 5.2.7 Displaying "Hello from task" on the Terminal Execute the following command to display messages from the JTAG-UART implemented in the design on the host terminal. Press "CTRL+C" to exit. juart-terminal Output: juart-terminal: connected to hardware target using JTAG UART on cable juart-terminal: "USB-BlasterII [1-6.1]", device 1, instance 0 juart-terminal: (Use the IDE stop button or Ctrl-C to terminate) Hello from main... Hello from task1: 0 Hello from task2: 0 Hello from task3: 0 Hello from task3: 1 Hello from task2: 1 Hello from task3: 2 Hello from task1: 1 Hello from task3: 3 Hello from task2: 2 Hello from task3: 4 Hello from task3: 5 Hello from task2: 3 Hello from task1: 2 Hello from task3: 6 ..... ..... ..... Hello from task2: 31 Hello from task1: 19 juart-terminal: exiting due to ^C on host 5.3 FreeRTOS™ Edition Next, let's compile and run the FreeRTOS™ sample. 5.3.1 Generating Board Support Package (BSP) Use the following command to generate a BSP for FreeRTOS™. The BSP settings file sw/bsp_freertos/settings.bsp is prepared. Specify freertos for the Type. niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/sys.qsys --type=freertos sw/bsp_freertos/settings.bsp Output: 2023.11.28.01:10:14 Info: Searching for BSP components with category: os_software_element 2023.11.28.01:10:16 Info: Creating BSP settings. 2023.11.28.01:10:16 Info: Searching for BSP components with category: driver_element 2023.11.28.01:10:16 Info: Searching for BSP components with category: software_package_element 2023.11.28.01:10:16 Info: Loading drivers from ensemble report. 2023.11.28.01:10:16 Info: Finished loading drivers from ensemble report. 2023.11.28.01:10:16 Info: Evaluating default script "/home/ubuntu_usr/intelFPGA_pro/23.3/quartus/../niosv/scripts/bsp-defaults/bsp-set-defaults.tcl". 2023.11.28.01:10:16 Info: Tcl message: "STDIO character device is jtag_uart" 2023.11.28.01:10:16 Info: Tcl message: "System timer device is cpu" 2023.11.28.01:10:16 Info: Tcl message: "Default linker sections mapped to ram" 2023.11.28.01:10:16 Info: Tcl message: "No bootloader located at the reset address." 2023.11.28.01:10:16 Info: Tcl message: "Application ELF allowed to contain code at the reset address." 2023.11.28.01:10:16 Info: Tcl message: "The alt_load() facility is enabled." 2023.11.28.01:10:16 Info: Tcl message: "The .rwdata section is copied into RAM by alt_load()." 2023.11.28.01:10:16 Info: Saving BSP settings file. 2023.11.28.01:10:16 Info: Default memory regions will not be persisted in BSP Settings File. 2023.11.28.01:10:16 Info: Generated file "/home/ubuntu_usr/ws/ws_pro/niosv_hello_world/top_project/sw/bsp_freertos/settings.bsp" 2023.11.28.01:10:16 Info: Generating BSP files in "/home/ubuntu_usr/ws/ws_pro/niosv_hello_world/top_project/sw/bsp_freertos" 2023.11.28.01:10:16 Info: Default memory regions will not be persisted in BSP Settings File. 2023.11.28.01:10:16 Info: Generated file "/home/ubuntu_usr/ws/ws_pro/niosv_hello_world/top_project/sw/bsp_freertos/settings.bsp" 2023.11.28.01:10:16 Info: Finished generating BSP files. Total time taken = 2 seconds 5.3.2 Generating CMafileLists.txt Generate CMakefileLists.txt. Use the application directory and source code for FreeRTOS™ available in sw/app_freertos. niosv-app --bsp-dir=sw/bsp_freertos --app-dir=sw/app_freertos --srcs=sw/app_freertos --elf-name=hello_freertos.elf Output: 2023.11.28.01:12:10 Info: Elf name is set to "hello_freertos.elf". 2023.11.28.01:12:10 Info: Source file "hello_freertos.c" added from directory "sw/app_freertos". 2023.11.28.01:12:10 Info: "sw/app_freertos/CMakeLists.txt" was generated. 5.3.3 Generating Makefile Execute the following command to generate a Makefile from CMakeLists.txt. You need to delete sw/app_freertos/build/CMakeCache.txt if it's the first generation. rm sw/app_freertos/build/CMakeCache.txt Then generate the Makefile. cmake -S sw/app_freertos -G "Unix Makefiles" -B sw/app_freertos/build Output: -- Defaulting build type to Debug. -- The ASM compiler identification is GNU -- Found assembler: /home/ubuntu_usr/intelFPGA_pro/23.3/riscfree/toolchain/riscv32-unknown-elf/bin/riscv32-unknown-elf-gcc -- The C compiler identification is GNU 12.1.0 -- Detecting C compiler ABI info -- Detecting C compiler ABI info - done -- Check for working C compiler: /home/ubuntu_usr/intelFPGA_pro/23.3/riscfree/toolchain/riscv32-unknown-elf/bin/riscv32-unknown-elf-gcc - skipped -- Detecting C compile features -- Detecting C compile features - done -- The CXX compiler identification is GNU 12.1.0 -- Detecting CXX compiler ABI info -- Detecting CXX compiler ABI info - done -- Check for working CXX compiler: /home/ubuntu_usr/intelFPGA_pro/23.3/riscfree/toolchain/riscv32-unknown-elf/bin/riscv32-unknown-elf-g++ - skipped -- Detecting CXX compile features -- Detecting CXX compile features - done -- Configuring done (0.2s) -- Generating done (0.0s) -- Build files have been written to: /home/ubuntu_usr/ws/ws_pro/niosv_hello_world/top_project/sw/app_freertos/build 5.3.4 Generating hello_ucosii.elf Execute the following command to generate hello_freertos.elf. make -C sw/app_freertos/build Output: make: Entering directory '/home/ubuntu_usr/ws/ws_pro/niosv_hello_world/top_project/sw/app_freertos/build' [ 1%] Building ASM object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_log_macro.S.obj [ 2%] Building ASM object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_mcount.S.obj [ 3%] Building ASM object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/crt0.S.obj [ 4%] Building ASM object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/machine_trap.S.obj [ 5%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/FREERTOS/src/alt_env_lock.c.obj [ 6%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/FREERTOS/src/alt_malloc_lock.c.obj [ 7%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/FREERTOS/src/heap_wrapper.c.obj [ 8%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/FreeRTOS-Kernel/croutine.c.obj [ 9%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/FreeRTOS-Kernel/event_groups.c.obj [ 10%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/FreeRTOS-Kernel/list.c.obj [ 11%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/FreeRTOS-Kernel/portable/GCC/RISC-V/port.c.obj [ 12%] Building ASM object bsp_freertos/CMakeFiles/freertos_bsp.dir/FreeRTOS-Kernel/portable/GCC/RISC-V/portASM.S.obj [ 13%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/FreeRTOS-Kernel/queue.c.obj [ 14%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/FreeRTOS-Kernel/stream_buffer.c.obj [ 15%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/FreeRTOS-Kernel/tasks.c.obj [ 16%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/FreeRTOS-Kernel/timers.c.obj [ 17%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_alarm_start.c.obj [ 18%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_busy_sleep.c.obj [ 19%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_close.c.obj [ 20%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_dcache_flush.c.obj [ 21%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_dcache_flush_all.c.obj [ 22%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_dcache_flush_no_writeback.c.obj [ 23%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_dev.c.obj [ 24%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_dev_llist_insert.c.obj [ 25%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_dma_rxchan_open.c.obj [ 26%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_dma_txchan_open.c.obj [ 27%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_do_ctors.c.obj [ 28%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_do_dtors.c.obj [ 29%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_environ.c.obj [ 30%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_errno.c.obj [ 31%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_execve.c.obj [ 32%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_exit.c.obj [ 33%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_fcntl.c.obj [ 34%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_fd_lock.c.obj [ 35%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_fd_unlock.c.obj [ 36%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_find_dev.c.obj [ 37%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_find_file.c.obj [ 38%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_flash_dev.c.obj [ 39%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_fork.c.obj [ 40%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_fs_reg.c.obj [ 41%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_fstat.c.obj [ 42%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_get_fd.c.obj [ 43%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_getchar.c.obj [ 44%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_getpid.c.obj [ 45%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_gettod.c.obj [ 46%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_gmon.c.obj [ 47%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_icache_flush.c.obj [ 48%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_icache_flush_all.c.obj [ 49%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_iic.c.obj [ 50%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_iic_isr_register.c.obj [ 50%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_instruction_exception_register.c.obj [ 51%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_io_redirect.c.obj [ 52%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_ioctl.c.obj [ 53%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_irq_handler.c.obj [ 54%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_isatty.c.obj [ 55%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_kill.c.obj [ 56%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_link.c.obj [ 57%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_load.c.obj [ 58%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_log_printf.c.obj [ 59%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_lseek.c.obj [ 60%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_main.c.obj [ 61%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_open.c.obj [ 62%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_printf.c.obj [ 63%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_putchar.c.obj [ 64%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_putcharbuf.c.obj [ 65%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_putstr.c.obj [ 66%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_read.c.obj [ 67%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_release_fd.c.obj [ 68%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_remap_cached.c.obj [ 69%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_remap_uncached.c.obj [ 70%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_rename.c.obj [ 71%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_sbrk.c.obj [ 72%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_settod.c.obj [ 73%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_stat.c.obj [ 74%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_tick.c.obj [ 75%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_times.c.obj [ 76%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_tls.c.obj [ 77%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_uncached_free.c.obj [ 78%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_uncached_malloc.c.obj [ 79%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_unlink.c.obj [ 80%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_usleep.c.obj [ 81%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_wait.c.obj [ 82%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/alt_write.c.obj [ 83%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/intel_fpga_api_cmn_dfl.c.obj [ 84%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/intel_fpga_api_cmn_inf.c.obj [ 85%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/intel_fpga_api_cmn_msg.c.obj [ 86%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/intel_fpga_api_niosv.c.obj [ 87%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/intel_fpga_platform_api_niosv.c.obj [ 88%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/intel_niosv_irq.c.obj [ 89%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/mtimer.c.obj [ 90%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/HAL/src/os_cpu_c.c.obj [ 91%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/alt_sys_init.c.obj [ 92%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/drivers/src/altera_avalon_jtag_uart_fd.c.obj [ 93%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/drivers/src/altera_avalon_jtag_uart_init.c.obj [ 94%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/drivers/src/altera_avalon_jtag_uart_ioctl.c.obj [ 95%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/drivers/src/altera_avalon_jtag_uart_read.c.obj [ 96%] Building C object bsp_freertos/CMakeFiles/freertos_bsp.dir/drivers/src/altera_avalon_jtag_uart_write.c.obj [ 97%] Linking C static library libfreertos_bsp.a [ 97%] Built target freertos_bsp [ 98%] Building C object CMakeFiles/hello_freertos.elf.dir/hello_freertos.c.obj [ 99%] Linking C executable hello_freertos.elf [ 99%] Built target hello_freertos.elf [ 99%] Creating hello_freertos.elf.objdump. [ 99%] Built target create-objdump [100%] Reporting memory available for stack + heap in hello_freertos.elf. hello_freertos.elf * 237.03 KB - Program size (code + initialized data). * 11.88 KB - Free for stack + heap. [100%] Built target niosv-stack-report make: Leaving directory '/home/ubuntu_usr/ws/ws_pro/niosv_hello_world/top_project/sw/app_freertos/build' 5.3.5 Downloading hello_freertos.elf File Download the created ELF file to the target's RAM using the following command. niosv-download sw/app_freertos/build/hello_freertos.elf Output: INFO: Generating OpenOCD config file. Running "openocd-cfg-gen /tmp/tmpr36gcpa0/niosv.cfg". /bin/bash: /home/ubuntu_usr/intelFPGA_pro/23.3/niosv/bin/../../quartus/linux64/libtinfo.so.6: no version information available (required by /bin/bash) INFO: Starting OpenOCD. Running "openocd -c tcl_port disabled -c gdb_port 0 -c telnet_port 0 -f /tmp/tmpr36gcpa0/niosv.cfg". [OpenOCD output] Open On-Chip Debugger 0.11.0-R22.4 [OpenOCD output] Licensed under GNU GPL v2 [OpenOCD output] For bug reports, read [OpenOCD output] http://openocd.org/doc/doxygen/bugs.html [OpenOCD output] Info : only one transport option; autoselect 'jtag' [OpenOCD output] Info : Application name is OpenOCD.20231128011822 [OpenOCD output] Info : Attempting to find 'USB-BlasterII [1-6.1]' [OpenOCD output] [OpenOCD output] Info : Cable 1: device_name=(null), hw_name=USB-BlasterII, server=(null), port=1-6.1, chain_id=0x55938b2e8420, persistent_id=1, chain_type=1, features=2048, server_version_info=(null) [OpenOCD output] Info : TAP position 0 (2E050DD) has 3 SLD nodes [OpenOCD output] Info : node 0 idcode=00486E00 position_n=0 [OpenOCD output] Info : node 1 idcode=08986E00 position_n=0 [OpenOCD output] Info : node 2 idcode=0C006E00 position_n=0 [OpenOCD output] Info : TAP position 1 (4BA00477) has 0 SLD nodes [OpenOCD output] Info : Discovered 2 TAP devices [OpenOCD output] Info : Detected device (tap_position=0) device_id=02e050dd, instruction_length=10, features=4, device_name=10AS066H(1|2|3|3E2|4|4E2)/.. [OpenOCD output] Info : Found an Intel device at tap_position 0.Currently assuming it is SLD Hub [OpenOCD output] Info : Detected device (tap_position=1) device_id=4ba00477, instruction_length=4, features=0, device_name=SOCVHPS [OpenOCD output] Info : Found a ARM device at tap_position 1. Currently assume it is JTAG-DP capable [OpenOCD output] Info : This adapter doesn't support configurable speed [OpenOCD output] Info : JTAG tap: tap_02E050DD.0 tap/device found: 0x02e050dd (mfg: 0x06e (Altera), part: 0x2e05, ver: 0x0) [OpenOCD output] Info : JTAG tap: tap_4BA00477.0 tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) [OpenOCD output] Info : JTAG tap: tap_02E050DD.0 Parent Tap found: 0x02e050dd (mfg: 0x06e (Altera), part: 0x2e05, ver: 0x0) [OpenOCD output] Info : Virtual Tap/SLD node 0x08986E00 found at tap position 0 vtap position 1 [OpenOCD output] Info : datacount=2 progbufsize=8 [OpenOCD output] Info : Examined RISC-V core; found 1 harts [OpenOCD output] Info : hart 0: XLEN=32, misa=0x40000101 [OpenOCD output] Info : starting gdb server for tap_02E050DD.0.niosv_0.cpu on 0 [OpenOCD output] Info : Listening on port 41985 for gdb connections INFO: Found gdb port 41985 [OpenOCD output] Ready for Remote Connections [OpenOCD output] Info : tcl server disabled [OpenOCD output] Info : Listening on port 38931 for telnet connections INFO: Found telnet port 38931 INFO: OpenOCD is ready. INFO: Loading image via GDB. Running "riscv32-unknown-elf-gdb -batch -ex set arch riscv:rv32 -ex set remotetimeout 60 -ex target extended-remote localhost:41985 -ex load sw/app_freertos/build/hello_freertos.elf -ex set $mstatus &= ~(0x00000088)". The target architecture is set to "riscv:rv32". warning: No executable has been specified and target does not support determining executable automatically. Try using the "file" command. 0x000028dc in ?? () Loading section .entry, size 0x20 lma 0x0 Loading section .exceptions, size 0x29c lma 0x20 Loading section .text, size 0x24954 lma 0x300 Loading section .rodata, size 0x1080 lma 0x24c60 Loading section .rwdata, size 0x1c0c lma 0x278ec Start address 0x00000594, load size 161948 Transfer rate: 159 KB/sec, 11567 bytes/write. [Inferior 1 (Remote target) detached] 5.3.6 Resetting the CPU with ISSP (In-System Source & Probe) Execute the following command to toggle the reset signal and reset the design. quartus_stp -t scripts/toggle_issp.tcl Output: Info: ******************************************************************* Info: Running Quartus Prime Signal Tap Info: Version 23.3.0 Build 104 09/20/2023 SC Pro Edition Info: Copyright (C) 2023 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the Intel FPGA Software License Subscription Agreements Info: on the Quartus Prime software download page. Info: Processing started: Tue Nov 28 01:28:59 2023 Info: System process ID: 13460 Info: Command: quartus_stp -t scripts/toggle_issp.tcl Info: The application is running in 'DNI' mode. /bin/bash: /home/ubuntu_usr/intelFPGA_pro/23.3/quartus/linux64/libtinfo.so.6: no version information available (required by /bin/bash) Info (23030): Evaluation of Tcl script scripts/toggle_issp.tcl was successful Info: Quartus Prime Signal Tap was successful. 0 errors, 0 warnings Info: Peak virtual memory: 737 megabytes Info: Processing ended: Tue Nov 28 01:29:00 2023 Info: Elapsed time: 00:00:01 Info: System process ID: 13460 5.3.7 Displaying "Hello from task" on the Terminal Run the following command to display messages from the JTAG-UART implemented in the design on the host terminal. Press "CTRL+C" to exit. juart-terminal Output: juart-terminal: connected to hardware target using JTAG UART on cable juart-terminal: "USB-BlasterII [1-6.1]", device 1, instance 0 juart-terminal: (Use the IDE stop button or Ctrl-C to terminate) Hello FreeRTOS from main... Hello from task1: 0 Hello from task2: 0 Hello from task3: 0 Hello from task3: 1 Hello from task2: 1 Hello from task3: 2 Hello from task1: 1 Hello from task3: 3 Hello from task2: 2 Hello from task3: 4 Hello from task2: 3 Hello from task1: 2 Hello from task2: 4 Hello from task1: 3 Hello from task1: 4 juart-terminal: exiting due to ^C on host 6. Summary This concludes the updated article for the Nios® V processor Installation and Hello World Execution. It should be evident that various aspects have been updated from Intel® Quartus® Prime Pro Edition 21.3 to Intel® Quartus® Prime Pro Edition 23.3. I encourage you to try running the Example Design yourself. References Nios® V processor Boot, Simulation, and Debug Edition Nios® V Embedded Processor Design Handbook Nios® V Processor Reference Manual NiosV tool setup for Eclipse CDT and OpenOCD RISC-V Unprivileged Spec v.20191213 RISC-V Privileged Spec v.20190608 RISC-V External Debug Support v.0.13.2 AMBA AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite ACE and ACE-Lite Notices & Disclaimers Intel technologies may require enabled hardware, software, or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from the course of performance, course of dealing, or usage in trade. Nios is a trademark of Intel Corporation or its subsidiaries.Debugger wont connect to NIOS II hello world on Cyclone GX development board
The Cyclone 10GX seems to configure from the programmer but Eclipse fails to connect though the embedded download cable. I only got this far by checking the 'Ignore mismatched system ID' and 'Ignore mismatched system timestamp' in the Target connection dialog, so I guess I need to fix that somehow. The programmer JTAG auto-detect looks like this. Thanks in advanceNiosV
Hi I am in the process of converting a MAX10 Nios2 design to a MAX10 NiosV. It boots from Flash loaded into DDR All is good with the compiling apart from I need to convert the elf file to a hex file. Nios2 was done with Eclipse tools and it created the script alt-file-convert.exe -I elf32-littlenios2 -O hex --input=app.elf --output=mem_init/ext_flash.hex --base=0x44000000 --end=0x45ffffff --reset=0x44430000 --out-data-width=8 --boot="C:\intelfpga_lite\23.1std\nios2eds\components\altera_nios2\boot_loader_cfi.srec" Now i have to use NiosV command line to do the same, but the alt-file-convert.exe command doesnt exist. I think it may be something like this: elf2flash --input=sw/app/build/app.elf --output=sw/app/build/mem_init/ext_flash.hex --epcs –-offset 0x0 --end=0x45ffffff --boot="C:/intelFPGA_lite/23.1std/niosv/components/bootloader/niosv_g_bootloader" Note the --base and --reset that alt-file-convert.exe used can't be used with elf2flash - is that correct?
