Eclipse error when trying to run Nios II program from sdram

Good evening, i have this problem where i try to run the "hello world" template in Eclipse after having designed a nios II system in Platform Designer configured with the sdram as the exception and reset vector. Eclipse says:

"Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Processor is already paused
Initializing CPU cache (if present)
OK

Downloading 02000000 ( 0%)
Downloading 02007250 (76%)
Downloaded 29KB in 0.4s (72.5KB/s)

Verifying 02000000 ( 0%)
Verify failed between address 0x2000000 and 0x20057B7
Leaving target processor paused"

I'm working on a DE0-Nano board.

These are the warnings i get in Quartus prime 18.1 during compilation:

"

Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (12251): Test.accelerometer_spi_0: Interrupt sender accelerometer_spi_0.interrupt is not connected to an interrupt receiver
Warning (10238): Verilog Module Declaration warning at altera_up_accelerometer_spi_auto_init_ctrl.v(51): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "altera_up_accelerometer_spi_auto_init_ctrl"
Warning (10037): Verilog HDL or VHDL warning at test_new_sdram_controller_0.v(318): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at test_new_sdram_controller_0.v(328): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at test_new_sdram_controller_0.v(338): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at test_new_sdram_controller_0.v(682): conditional expression evaluates to a constant
Warning (10230): Verilog HDL assignment warning at test_accelerometer_spi_0.v(226): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at test_accelerometer_spi_0.v(241): truncated value with size 8 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at altera_up_accelerometer_spi_auto_init_ctrl.v(137): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at altera_up_accelerometer_spi_serial_bus_controller.v(215): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at altera_up_accelerometer_spi_slow_clock_generator.v(110): truncated value with size 32 to match size of target (4)
Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(742): object "aligned_addr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(743): object "aligned_byte_cnt" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(742): object "aligned_addr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(743): object "aligned_byte_cnt" assigned a value but never read
Warning (12241): 5 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "new_sdram_controller_0_wire_cke" is stuck at VCC
Warning (21074): Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "accelerometer_spi_0_external_interface_G_SENSOR_INT"
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Warning (176125): The input ports of the PLL test_altpll_1:altpll_1|test_altpll_1_altpll_u942:sd1|pll7 and the PLL test_altpll_0:altpll_0|test_altpll_0_altpll_m342:sd1|pll7 are mismatched, preventing the PLLs to be merged
Warning (176124): PLL test_altpll_1:altpll_1|test_altpll_1_altpll_u942:sd1|pll7 and PLL test_altpll_0:altpll_0|test_altpll_0_altpll_m342:sd1|pll7 have different input signals for input port ARESET
Critical Warning (176598): PLL "test_altpll_1:altpll_1|test_altpll_1_altpll_u942:sd1|pll7" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_R8"
Warning (332174): Ignored filter at test.sdc(9): CLOCK_50 could not be matched with a port
Warning (332049): Ignored create_clock at test.sdc(9): Argument <targets> is an empty collection
Info (332050): create_clock -period 20 [get_ports CLOCK_50]
Warning (332087): The master clock for this clock assignment could not be derived. Clock: altpll_0|sd1|pll7|clk[0] was not created.
Warning (332035): No clocks found on or feeding the specified source node: altpll_0|sd1|pll7|inclk[0]
Warning (332087): The master clock for this clock assignment could not be derived. Clock: altpll_1|sd1|pll7|clk[0] was not created.
Warning (332035): No clocks found on or feeding the specified source node: altpll_1|sd1|pll7|inclk[0]
Warning (332060): Node: clk_clk was determined to be a clock but was found without an associated clock assignment.
Info (13166): Register test_accelerometer_spi_0:accelerometer_spi_0|altera_up_accelerometer_spi_serial_bus_controller:Serial_Bus_Controller|s_serial_protocol.STATE_2_START_BIT is being clocked by clk_clk
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
Warning (332056): Node: altpll_0|sd1|pll7|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (332056): Node: altpll_1|sd1|pll7|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (176250): Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Warning (176251): Ignoring some wildcard destinations of fast I/O register assignments
Info (176252): Wildcard assignment "Fast Output Enable Register=ON" to "oe" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[9]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[8]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[7]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[6]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[5]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[4]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[3]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[2]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[1]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[15]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[14]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[13]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[12]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[11]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[10]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[0]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_cmd[2]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_cmd[1]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_cmd[0]" matches multiple destination nodes -- some destinations are not valid targets for this assignment
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Warning (169177): 20 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
Info (169178): Pin accelerometer_spi_0_external_interface_G_SENSOR_INT uses I/O standard 3.3-V LVTTL at M2
Info (169178): Pin accelerometer_spi_0_external_interface_I2C_SDAT uses I/O standard 3.3-V LVTTL at F1
Info (169178): Pin new_sdram_controller_0_wire_dq[0] uses I/O standard 3.3-V LVTTL at G2
Info (169178): Pin new_sdram_controller_0_wire_dq[1] uses I/O standard 3.3-V LVTTL at G1
Info (169178): Pin new_sdram_controller_0_wire_dq[2] uses I/O standard 3.3-V LVTTL at L8
Info (169178): Pin new_sdram_controller_0_wire_dq[3] uses I/O standard 3.3-V LVTTL at K5
Info (169178): Pin new_sdram_controller_0_wire_dq[4] uses I/O standard 3.3-V LVTTL at K2
Info (169178): Pin new_sdram_controller_0_wire_dq[5] uses I/O standard 3.3-V LVTTL at J2
Info (169178): Pin new_sdram_controller_0_wire_dq[6] uses I/O standard 3.3-V LVTTL at J1
Info (169178): Pin new_sdram_controller_0_wire_dq[7] uses I/O standard 3.3-V LVTTL at R7
Info (169178): Pin new_sdram_controller_0_wire_dq[8] uses I/O standard 3.3-V LVTTL at T4
Info (169178): Pin new_sdram_controller_0_wire_dq[9] uses I/O standard 3.3-V LVTTL at T2
Info (169178): Pin new_sdram_controller_0_wire_dq[10] uses I/O standard 3.3-V LVTTL at T3
Info (169178): Pin new_sdram_controller_0_wire_dq[11] uses I/O standard 3.3-V LVTTL at R3
Info (169178): Pin new_sdram_controller_0_wire_dq[12] uses I/O standard 3.3-V LVTTL at R5
Info (169178): Pin new_sdram_controller_0_wire_dq[13] uses I/O standard 3.3-V LVTTL at P3
Info (169178): Pin new_sdram_controller_0_wire_dq[14] uses I/O standard 3.3-V LVTTL at N3
Info (169178): Pin new_sdram_controller_0_wire_dq[15] uses I/O standard 3.3-V LVTTL at K1
Info (169178): Pin clk_clk uses I/O standard 3.3-V LVTTL at R8
Info (169178): Pin reset_reset_n uses I/O standard 3.3-V LVTTL at B9
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (332174): Ignored filter at test.sdc(9): CLOCK_50 could not be matched with a port
Warning (332049): Ignored create_clock at test.sdc(9): Argument <targets> is an empty collection
Info (332050): create_clock -period 20 [get_ports CLOCK_50]
Warning (332087): The master clock for this clock assignment could not be derived. Clock: altpll_1|sd1|pll7|clk[0] was not created.
Warning (332035): No clocks found on or feeding the specified source node: altpll_1|sd1|pll7|inclk[0]
Warning (332087): The master clock for this clock assignment could not be derived. Clock: altpll_0|sd1|pll7|clk[0] was not created.
Warning (332035): No clocks found on or feeding the specified source node: altpll_0|sd1|pll7|inclk[0]
Warning (332060): Node: clk_clk was determined to be a clock but was found without an associated clock assignment.
Info (13166): Register test_accelerometer_spi_0:accelerometer_spi_0|altera_up_accelerometer_spi_serial_bus_controller:Serial_Bus_Controller|s_serial_protocol.STATE_2_START_BIT is being clocked by clk_clk
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
Warning (332056): Node: altpll_1|sd1|pll7|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (332056): Node: altpll_0|sd1|pll7|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (332087): The master clock for this clock assignment could not be derived. Clock: altpll_1|sd1|pll7|clk[0] was not created.
Warning (332035): No clocks found on or feeding the specified source node: altpll_1|sd1|pll7|inclk[0]
Warning (332087): The master clock for this clock assignment could not be derived. Clock: altpll_0|sd1|pll7|clk[0] was not created.
Warning (332035): No clocks found on or feeding the specified source node: altpll_0|sd1|pll7|inclk[0]
Warning (332060): Node: clk_clk was determined to be a clock but was found without an associated clock assignment.
Info (13166): Register test_accelerometer_spi_0:accelerometer_spi_0|altera_up_accelerometer_spi_serial_bus_controller:Serial_Bus_Controller|s_serial_protocol.STATE_2_START_BIT is being clocked by clk_clk
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
Warning (332056): Node: altpll_1|sd1|pll7|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (332056): Node: altpll_0|sd1|pll7|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (332087): The master clock for this clock assignment could not be derived. Clock: altpll_1|sd1|pll7|clk[0] was not created.
Warning (332035): No clocks found on or feeding the specified source node: altpll_1|sd1|pll7|inclk[0]
Warning (332087): The master clock for this clock assignment could not be derived. Clock: altpll_0|sd1|pll7|clk[0] was not created.
Warning (332035): No clocks found on or feeding the specified source node: altpll_0|sd1|pll7|inclk[0]
Warning (332060): Node: clk_clk was determined to be a clock but was found without an associated clock assignment.
Info (13166): Register test_accelerometer_spi_0:accelerometer_spi_0|altera_up_accelerometer_spi_serial_bus_controller:Serial_Bus_Controller|s_serial_protocol.STATE_2_START_BIT is being clocked by clk_clk
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
Warning (332056): Node: altpll_1|sd1|pll7|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (332056): Node: altpll_0|sd1|pll7|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000

"